Simulation Results: otbn

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.20 %
  • code
  • 95.35 %
  • assert
  • 89.80 %
  • func
  • 97.46 %
  • block
  • 99.40 %
  • line
  • 99.54 %
  • branch
  • 92.51 %
  • toggle
  • 91.79 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 81.026us 1 1 100.00
single_binary 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 18.147us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 13.367us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 4.000s 24.105us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 25.546us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 48.425us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 13.367us 1 1 100.00
otbn_csr_aliasing 4.000s 25.546us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 39.000s 2245.466us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 16.000s 1184.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 29.000s 83.182us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 492.658us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 63.000s 963.778us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 10.000s 110.938us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 39.396us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 0.667s 0.000us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 17.699us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 55.456us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 20.210us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 473.479us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 473.479us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 18.147us 1 1 100.00
otbn_csr_rw 3.000s 13.367us 1 1 100.00
otbn_csr_aliasing 4.000s 25.546us 1 1 100.00
otbn_same_csr_outstanding 4.000s 21.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 18.147us 1 1 100.00
otbn_csr_rw 3.000s 13.367us 1 1 100.00
otbn_csr_aliasing 4.000s 25.546us 1 1 100.00
otbn_same_csr_outstanding 4.000s 21.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 24.680us 1 1 100.00
otbn_dmem_err 7.000s 18.086us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 9.000s 209.605us 1 1 100.00
otbn_controller_ispr_rdata_err 41.000s 288.426us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 35.395us 1 1 100.00
otbn_urnd_err 6.000s 16.882us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 23.901us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 50.822us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 50.001us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
otbn_tl_intg_err 15.000s 200.452us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 22.000s 395.074us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 81.026us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 18.086us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 24.680us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 200.452us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 39.396us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 24.680us 1 1 100.00
otbn_dmem_err 7.000s 18.086us 1 1 100.00
otbn_zero_state_err_urnd 0.667s 0.000us 0 1 0.00
otbn_illegal_mem_acc 8.000s 23.901us 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 24.680us 1 1 100.00
otbn_dmem_err 7.000s 18.086us 1 1 100.00
otbn_zero_state_err_urnd 0.667s 0.000us 0 1 0.00
otbn_illegal_mem_acc 8.000s 23.901us 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 39.396us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 24.680us 1 1 100.00
otbn_dmem_err 7.000s 18.086us 1 1 100.00
otbn_zero_state_err_urnd 0.667s 0.000us 0 1 0.00
otbn_illegal_mem_acc 8.000s 23.901us 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 53.665us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 40.128us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 47.000s 215.396us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 47.000s 215.396us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 16.293us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 11.000s 264.316us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 36.534us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 36.534us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 93.279us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 63.000s 963.778us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 38.564us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 12.000s 91.181us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 375.000s 2727.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 369.000s 5246.404us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 193.050us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 18981731889591419013456035452241742205442838740181993218938611904957394679707 648
UVM_INFO @ 5246404356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_zero_state_err_urnd 34476917355785186586829150641791034472442623602320841785362945490202844887196 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1