Simulation Results: otp_ctrl

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 68.66 %
  • code
  • 68.18 %
  • assert
  • 91.47 %
  • func
  • 46.32 %
  • line
  • 86.23 %
  • branch
  • 82.85 %
  • cond
  • 84.69 %
  • toggle
  • 56.43 %
  • FSM
  • 30.70 %
Validation stages
V1
88.89%
V2
55.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.030s 210.707us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 3.880s 184.875us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.590s 148.313us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.630s 167.183us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.700s 353.078us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 14.120s 5530.939us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.220s 91.311us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.630s 167.183us 1 1 100.00
otp_ctrl_csr_aliasing 14.120s 5530.939us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.570s 158.900us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.830s 157.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 123.300s 13330.339us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.650s 62.948us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 6.810s 218.447us 1 1 100.00
otp_ctrl_check_fail 6.910s 454.584us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 8.600s 4292.882us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 10.080s 2222.940us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 5.540s 647.410us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 10.680s 480.176us 0 1 0.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.710s 3171.397us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.830s 2541.812us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 12.870s 5108.149us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 6.140s 422.977us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.180s 645.768us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.290s 145.001us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.740s 574.950us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.740s 574.950us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.590s 148.313us 1 1 100.00
otp_ctrl_csr_rw 1.630s 167.183us 1 1 100.00
otp_ctrl_csr_aliasing 14.120s 5530.939us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.040s 199.804us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.590s 148.313us 1 1 100.00
otp_ctrl_csr_rw 1.630s 167.183us 1 1 100.00
otp_ctrl_csr_aliasing 14.120s 5530.939us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.040s 199.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
otp_ctrl_tl_intg_err 22.680s 3592.783us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 22.680s 3592.783us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 3.880s 184.875us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 3.880s 184.875us 0 1 0.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
otp_ctrl_macro_errs 3.830s 2541.812us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
otp_ctrl_macro_errs 3.830s 2541.812us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.000s 184.753us 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.650s 62.948us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 6.910s 454.584us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 10.080s 2222.940us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 10.080s 2222.940us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 10.080s 2222.940us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 10.080s 2222.940us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 10.080s 2222.940us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 3.880s 184.875us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 10.080s 2222.940us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 3.880s 184.875us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 253.540s 62690.227us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 8.600s 4292.882us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 3.880s 184.875us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 3.880s 184.875us 0 1 0.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.830s 2541.812us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 64.350s 22352.359us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 3.870s 307.331us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_check_fail 24477781593328041227620712485179452590209006651367690842470433871954560985845 5671
UVM_INFO @ 454583538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51559802076400961441279813056526543923705870414955113158730285446680327397623 1954
UVM_INFO @ 307331213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 19602457586504659225264878275654933682739844909409032893407961240579870215429 7494
UVM_INFO @ 422977060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_smoke 107538544129108512780617911114565875279365137392352981233501338063902277118396 4250
UVM_INFO @ 184874724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 7206251247527881682064326858766123150587781735712609666424519281988602180134 1937
UVM_INFO @ 62947894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_parallel_lc_req 5828966541028840919847626744385351532086674455522424919768706420666676806845 8477
UVM_INFO @ 480176465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 90263377832304267945410014486566950475214780924860837768140652249789273283275 2803
UVM_INFO @ 647410359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_dai_lock 77293890135237858596015441171639222907374894836426128057761256036286358436883 7574
UVM_INFO @ 2222940021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 22659965847613397055423528249799282021633087625794130414097728306586258274707 13602
UVM_INFO @ 5108149405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 36859725637207527307916720459172110134047383902464008293266894401885546762842 112657
UVM_INFO @ 13330339317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 66212151287259035875421934055854576344218136987399693105123136218763858723662 89
UVM_INFO @ 22352359433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 80068861994045408018424313770711484491506238129349856087123405270093666364036 2622
UVM_INFO @ 2541811927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---