Simulation Results: rom_ctrl/64kb

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 92.91 %
  • assert
  • 96.65 %
  • func
  • 97.41 %
  • block
  • 95.61 %
  • line
  • 96.00 %
  • branch
  • 93.28 %
  • toggle
  • 87.12 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 252.448us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 680.636us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 293.175us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 1341.173us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 3715.149us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 581.781us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 293.175us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 3715.149us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.000s 292.660us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 369.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.000s 2617.027us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.000s 3106.180us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.000s 8606.195us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 2094.975us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 699.630us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 699.630us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 680.636us 1 1 100.00
rom_ctrl_csr_rw 5.000s 293.175us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 3715.149us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 205.553us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 680.636us 1 1 100.00
rom_ctrl_csr_rw 5.000s 293.175us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 3715.149us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 205.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 4255.167us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 98.000s 1228.210us 1 1 100.00
rom_ctrl_tl_intg_err 40.000s 2792.325us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 1228.210us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 1228.210us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 1228.210us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 98.000s 1228.210us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 252.448us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 252.448us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 252.448us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 40.000s 2792.325us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
rom_ctrl_kmac_err_chk 12.000s 8606.195us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.000s 23600.782us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 4255.167us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 1228.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 54.000s 11552.203us 1 1 100.00