Simulation Results: rstmgr

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.64 %
  • code
  • 99.12 %
  • assert
  • 97.44 %
  • func
  • 93.37 %
  • line
  • 99.09 %
  • branch
  • 99.43 %
  • cond
  • 98.64 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.070s 57.530us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.220s 92.610us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.810s 35.721us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.150s 66.715us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.310s 40.371us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.710s 101.304us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.810s 35.721us 1 1 100.00
rstmgr_csr_aliasing 1.310s 40.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.480s 161.024us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.320s 43.862us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.130s 49.255us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.480s 590.639us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.480s 590.639us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.480s 590.639us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.480s 590.639us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.100s 2081.449us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.170s 37.507us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.360s 42.893us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.360s 42.893us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.220s 92.610us 1 1 100.00
rstmgr_csr_rw 0.810s 35.721us 1 1 100.00
rstmgr_csr_aliasing 1.310s 40.371us 1 1 100.00
rstmgr_same_csr_outstanding 1.310s 37.290us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.220s 92.610us 1 1 100.00
rstmgr_csr_rw 0.810s 35.721us 1 1 100.00
rstmgr_csr_aliasing 1.310s 40.371us 1 1 100.00
rstmgr_same_csr_outstanding 1.310s 37.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 15.500s 3433.209us 1 1 100.00
rstmgr_tl_intg_err 2.700s 391.763us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 15.500s 3433.209us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 15.500s 3433.209us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.700s 391.763us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.130s 65.249us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.510s 447.275us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.130s 292.131us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 15.500s 3433.209us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 35.721us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 35.721us 1 1 100.00