Simulation Results

Simulation Results: rv_dm/use_dmi_interface

12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.75 %

code
75.17 %

assert
96.12 %

func
91.96 %

block
89.69 %

line
89.47 %

branch
72.02 %

toggle
76.70 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	31.000s	1911.063us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	30.000s	697.485us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	33.000s	199.992us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	38.000s	10004.935us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	31.000s	536.810us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	32.000s	2159.213us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	46.000s	10244.567us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	59.000s	16254.864us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	56.000s	23581.436us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	729.789us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	174.174us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	921.051us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	32.000s	298.133us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	32.000s	409.200us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	34.000s	2624.388us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	30.000s	436.785us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	30.000s	258.583us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	729.789us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	600.275us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	34.000s	218.280us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	921.051us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	32.000s	92.630us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	34.000s	582.426us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	106.092us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	45.000s	1557.854us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	49.000s	6973.293us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	31.000s	84.124us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	49.000s	6973.293us	1	1	100.00
	rv_dm_csr_rw	31.000s	106.092us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	71.594us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	30.000s	104.114us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	31.000s	1911.063us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	32.000s	257.618us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	33.000s	148.462us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	32.000s	356.638us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	36.000s	473.525us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	33.000s	6516.092us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	34.000s	167.072us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	33.000s	2434.629us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	29.000s	69.038us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	32.000s	283.171us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	37.000s	3099.998us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	31.000s	111.124us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	32.000s	389.485us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	38.000s	7082.325us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	43.000s	2953.265us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	120.570us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	29.000s	220.949us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	50.274us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	31.000s	570.445us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	31.000s	570.445us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	49.000s	6973.293us	1	1	100.00
	rv_dm_csr_hw_reset	34.000s	582.426us	1	1	100.00
	rv_dm_csr_rw	31.000s	106.092us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	1232.299us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	49.000s	6973.293us	1	1	100.00
	rv_dm_csr_hw_reset	34.000s	582.426us	1	1	100.00
	rv_dm_csr_rw	31.000s	106.092us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	1232.299us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	31.000s	738.906us	1	1	100.00
	rv_dm_tl_intg_err	34.000s	2486.987us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	34.000s	2486.987us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	3099.998us	1	1	100.00
	rv_dm_debug_disabled	32.000s	73.180us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	3099.998us	1	1	100.00
	rv_dm_debug_disabled	32.000s	73.180us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	31.000s	1911.063us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	366.147us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	128.238us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	128.238us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	366.147us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	32.000s	971.713us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	336.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	94845849210687144852069852188798340389391407768228238190875865154718062911348	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10291
	rv_dm_bad_sba_tl_access	107536424297594345411578308056572547248628200818799105165400865775922400875249	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24123
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	20776295843783859880636469676829931128042714361004341234719743918308343882459	107	UVM_INFO @ 167072009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	112590545858426967994480860060091974172374509584416420106269046235970674707468	107	UVM_INFO @ 69037975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	74484370140272828323523321193600626109728548045201961029065141600817530425357	87	UVM_INFO @ 389485170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	48882946309872718054782501884103391168665000246201562682309918283953897009121	89	UVM_INFO @ 220949259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	18765785928838972520328671583091110728485561143002963241984117618589376045336	87	UVM_INFO @ 283170919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	41444530818952012006078084419874960106200566196024284450625866010787038975347	94	UVM_INFO @ 971713122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	593569530602047403366970396593991993116330133895749668386340611678302958764	87	UVM_INFO @ 298133139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	22434309609143624210699064513786821384927178171057119940498207628913669918042	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---