Simulation Results: rv_timer

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 792.790us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 54.807us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 44.782us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 1268.308us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 21.338us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 26.477us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 44.782us 1 1 100.00
rv_timer_csr_aliasing 2.000s 21.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 173.158us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 3749.872us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 45.000s 79962.244us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 45.000s 79962.244us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 449.123us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 14.559us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 49.155us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 62.110us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 62.110us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 54.807us 1 1 100.00
rv_timer_csr_rw 1.000s 44.782us 1 1 100.00
rv_timer_csr_aliasing 2.000s 21.338us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 51.415us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 54.807us 1 1 100.00
rv_timer_csr_rw 1.000s 44.782us 1 1 100.00
rv_timer_csr_aliasing 2.000s 21.338us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 51.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 284.468us 1 1 100.00
rv_timer_tl_intg_err 1.000s 91.897us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 91.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 77.318us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 173.420us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 20.000s 16409.265us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 75785252593813500393176521616701095189432141759499129107869994992612704736597 84
UVM_INFO @ 77317594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 6553458731119682735839901687530301012145525204379040331066114978242538915121 84
UVM_INFO @ 173420226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 74861840451308707347395678701463567330149573574085394438457303592526054603987 361
UVM_INFO @ 16409264529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---