Simulation Results: spi_device/1r1w

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.08 %
  • code
  • 90.70 %
  • assert
  • 94.51 %
  • func
  • 67.04 %
  • block
  • 98.22 %
  • line
  • 98.50 %
  • branch
  • 96.75 %
  • toggle
  • 81.09 %
  • FSM
  • 86.46 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 51.000s 10890.074us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 18.065us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 71.646us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 37.000s 10628.436us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 7.000s 7132.916us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 136.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 71.646us 1 1 100.00
spi_device_csr_aliasing 7.000s 7132.916us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 66.183us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 126.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 70.673us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 2.156us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.951us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 4.000s 105.767us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 4.000s 105.767us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.000s 38.709us 1 1 100.00
spi_device_tpm_sts_read 2.000s 27.245us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 12.000s 16776.476us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 8.000s 1341.305us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 30.856us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 30.856us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.000s 1160.780us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.000s 1160.780us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.000s 1160.780us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.000s 1160.780us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.000s 1160.780us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.000s 143.138us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 12.000s 946.320us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 12.000s 946.320us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 12.000s 946.320us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.000s 289.114us 1 1 100.00
spi_device_read_buffer_direct 16.000s 1181.616us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 12.000s 946.320us 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 21.000s 11098.443us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.000s 526.217us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.000s 526.217us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 51.000s 10890.074us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 73.000s 49789.583us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 2.000s 78.178us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 43.940us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 16.291us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 146.815us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 146.815us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 18.065us 1 1 100.00
spi_device_csr_rw 2.000s 71.646us 1 1 100.00
spi_device_csr_aliasing 7.000s 7132.916us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 302.243us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 18.065us 1 1 100.00
spi_device_csr_rw 2.000s 71.646us 1 1 100.00
spi_device_csr_aliasing 7.000s 7132.916us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 302.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 143.953us 1 1 100.00
spi_device_tl_intg_err 9.000s 195.301us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.000s 195.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 51.000s 24566.247us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 71136741218458618083573648193928475968574018014868092159034403078480283099160 87
UVM_ERROR @ 1254870 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[957] not found within the scope .
UVM_ERROR @ 1254870 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[957] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 22652356335645971020182948914420236951684729659497717061685591640766419174557 85
UVM_ERROR @ 2871260 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x848c99 [100001001000110010011001] vs 0x0 [0])
UVM_ERROR @ 2893260 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9280dd [100100101000000011011101] vs 0x0 [0])
UVM_ERROR @ 2921260 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xff912d [111111111001000100101101] vs 0x0 [0])
UVM_ERROR @ 2988260 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1290f0 [100101001000011110000] vs 0x0 [0])