Simulation Results: spi_host

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.47 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 2.000s 132.199us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 31.226us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 41.658us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 200.589us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 26.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 37.705us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 41.658us 1 1 100.00
spi_host_csr_aliasing 2.000s 26.577us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 47.281us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 28.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 33.045us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 108.421us 1 1 100.00
spi_host_error_cmd 1.000s 24.982us 1 1 100.00
spi_host_event 7.000s 1922.973us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 66.444us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 66.444us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 66.444us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 49.620us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 37.671us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 66.444us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 66.444us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 2.000s 132.199us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 2.000s 132.199us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 28.000s 8159.938us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 252.676us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 51.000s 3148.980us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 195.639us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 108.421us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 23.083us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 24.311us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 201.255us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 201.255us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 31.226us 1 1 100.00
spi_host_csr_rw 1.000s 41.658us 1 1 100.00
spi_host_csr_aliasing 2.000s 26.577us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 209.674us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 31.226us 1 1 100.00
spi_host_csr_rw 1.000s 41.658us 1 1 100.00
spi_host_csr_aliasing 2.000s 26.577us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 209.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 82.130us 1 1 100.00
spi_host_sec_cm 1.000s 275.863us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 82.130us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 160.000s 9155.550us 1 1 100.00