Simulation Results: sram_ctrl/main

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.48 %
  • code
  • 96.04 %
  • assert
  • 96.19 %
  • func
  • 94.20 %
  • block
  • 95.07 %
  • line
  • 95.70 %
  • branch
  • 92.38 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 376.181us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.808us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.865us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 123.210us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.555us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 734.665us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.865us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.555us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 214.000s 21762.596us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 48.000s 2700.233us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 23.000s 18648.737us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 148.000s 4601.046us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 138.000s 12659.684us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 37.000s 8300.587us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 18.000s 21607.123us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 2529.540us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 688.295us 1 1 100.00
sram_ctrl_partial_access_b2b 304.000s 106617.871us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 1398.561us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 1337.922us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 2476.811us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 3585.404us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1407.694us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 312.000s 108495.660us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 49.099us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 64.265us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 64.265us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.808us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.865us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.555us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 97.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.808us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.865us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.555us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 97.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 7345.087us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 192.815us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 155.220us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 192.815us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 155.220us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 3585.404us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 3585.404us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.865us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 2529.540us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 2529.540us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 2529.540us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 18.000s 21607.123us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 1373.133us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 7345.087us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 670.835us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 376.181us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 376.181us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 2529.540us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 192.815us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 18.000s 21607.123us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 192.815us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 192.815us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 376.181us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 192.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 1637.766us 1 1 100.00