Simulation Results: sram_ctrl/ret

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.55 %
  • code
  • 82.76 %
  • assert
  • 96.29 %
  • func
  • 95.60 %
  • block
  • 92.98 %
  • line
  • 93.99 %
  • branch
  • 88.11 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 49.171us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 26.581us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.278us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 1130.566us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.237us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 43.102us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 41.278us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.237us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 525.625us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 188.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 865.392us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 56.000s 1072.346us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 1459.102us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 23.000s 1649.491us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 848.307us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 1086.011us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 39.388us 1 1 100.00
sram_ctrl_partial_access_b2b 152.000s 23296.607us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 36.429us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 65.775us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 60.916us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 2104.217us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 50.457us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 27.000s 2604.806us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.636us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 97.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 97.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 26.581us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.278us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.237us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 46.467us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 26.581us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.278us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.237us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 46.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2291.923us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 787.908us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 276.360us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 787.908us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 276.360us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 2104.217us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 2104.217us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.278us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1086.011us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1086.011us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1086.011us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 848.307us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 175.690us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2291.923us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 45.722us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 49.171us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 49.171us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 1086.011us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 787.908us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 848.307us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 787.908us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 787.908us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 49.171us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 787.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 31.000s 5762.364us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (tl_host_driver.sv:119) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 102831691321692360206636691165413551717599531385427210444415856789235445447293 92
UVM_INFO @ 43101932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---