Simulation Results: uart

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.98 %
  • code
  • 77.29 %
  • assert
  • 95.97 %
  • func
  • 90.69 %
  • block
  • 98.33 %
  • line
  • 98.95 %
  • branch
  • 96.69 %
  • toggle
  • 88.53 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 707.627us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 12.909us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 46.086us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 117.107us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 21.207us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 54.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 46.086us 1 1 100.00
uart_csr_aliasing 1.000s 21.207us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 15.000s 10354.614us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 707.627us 1 1 100.00
uart_tx_rx 15.000s 10354.614us 1 1 100.00
parity_error 2 2 100.00
uart_intr 50.000s 36652.427us 1 1 100.00
uart_rx_parity_err 79.000s 57297.788us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 15.000s 10354.614us 1 1 100.00
uart_intr 50.000s 36652.427us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 50.000s 37154.961us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 23.000s 187185.701us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 92.000s 53251.922us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 50.000s 36652.427us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 50.000s 36652.427us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 50.000s 36652.427us 1 1 100.00
perf 1 1 100.00
uart_perf 276.000s 10328.126us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.000s 5894.636us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.000s 5894.636us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 16.000s 44690.922us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 3303.368us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 485.752us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.000s 4780.360us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 144.000s 20080.682us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 162.000s 119939.871us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 40.352us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 12.420us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.000s 49.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.000s 49.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 12.909us 1 1 100.00
uart_csr_rw 1.000s 46.086us 1 1 100.00
uart_csr_aliasing 1.000s 21.207us 1 1 100.00
uart_same_csr_outstanding 2.000s 40.831us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 12.909us 1 1 100.00
uart_csr_rw 1.000s 46.086us 1 1 100.00
uart_csr_aliasing 1.000s 21.207us 1 1 100.00
uart_same_csr_outstanding 2.000s 40.831us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 132.179us 1 1 100.00
uart_tl_intg_err 2.000s 117.092us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 117.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 17.000s 3959.759us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 77691658540026778469062608327470770986801214360705537102804105181698768428850 87
UVM_ERROR @ 42119068292 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 42119109959 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 43082242664 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 15, clk_pulses: 0
UVM_ERROR @ 43082284331 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty