Simulation Results: aes/gcm_masked

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 95.67 %
  • assert
  • 98.29 %
  • func
  • 68.06 %
  • block
  • 96.53 %
  • line
  • 97.67 %
  • branch
  • 91.59 %
  • toggle
  • 97.96 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 537.507us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 71.018us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 102.018us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 87.438us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 509.777us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 162.813us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 73.480us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 87.438us 1 1 100.00
aes_csr_aliasing 2.000s 162.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 71.018us 1 1 100.00
aes_config_error 3.000s 154.800us 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 71.018us 1 1 100.00
aes_config_error 3.000s 154.800us 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 76.217us 1 1 100.00
aes_b2b 9.000s 149.064us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 71.018us 1 1 100.00
aes_config_error 3.000s 154.800us 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
aes_alert_reset 5.000s 190.847us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 95.428us 1 1 100.00
aes_config_error 3.000s 154.800us 1 1 100.00
aes_alert_reset 5.000s 190.847us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 192.254us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 269.285us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 617.526us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 190.847us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 76.217us 1 1 100.00
aes_sideload 3.000s 134.667us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 196.817us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 25.000s 2106.690us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 188.920us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 72.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 148.213us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 148.213us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 102.018us 1 1 100.00
aes_csr_rw 2.000s 87.438us 1 1 100.00
aes_csr_aliasing 2.000s 162.813us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.378us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 102.018us 1 1 100.00
aes_csr_rw 2.000s 87.438us 1 1 100.00
aes_csr_aliasing 2.000s 162.813us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 71.832us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 57.547us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 57.547us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 57.547us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 57.547us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 206.051us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1094.139us 1 1 100.00
aes_tl_intg_err 3.000s 167.076us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 167.076us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 190.847us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 57.547us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 57.547us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 71.018us 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
aes_alert_reset 5.000s 190.847us 1 1 100.00
aes_core_fi 3.000s 99.819us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 188.920us 1 1 100.00
aes_config_error 3.000s 154.800us 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
aes_core_fi 3.000s 99.819us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 57.547us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 81.681us 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 76.217us 1 1 100.00
aes_sideload 3.000s 134.667us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.681us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.681us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 81.681us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 81.681us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 81.681us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 76.217us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 551.125us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
aes_ctr_fi 2.000s 73.081us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 551.125us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 551.125us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_ctr_fi 2.000s 73.081us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 551.125us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
aes_ctr_fi 2.000s 73.081us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 190.847us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
aes_ctr_fi 2.000s 73.081us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
aes_ctr_fi 2.000s 73.081us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_ctr_fi 2.000s 73.081us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_ghash_fi 2.000s 55.986us 1 1 100.00
aes_fi 4.000s 551.125us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 4.000s 551.125us 1 1 100.00
aes_control_fi 2.000s 50.078us 1 1 100.00
aes_cipher_fi 2.000s 61.840us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 22.000s 2536.310us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG 1 test run
aes_stress_all_with_rand_reset 67769266866331636767532335291406966055988673827663165271753768214164501444009 810
UVM_INFO @ 2536309806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---