Simulation Results: clkmgr

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.08 %
  • code
  • 68.52 %
  • assert
  • 89.26 %
  • func
  • 70.46 %
  • line
  • 81.76 %
  • branch
  • 86.53 %
  • cond
  • 78.76 %
  • toggle
  • 95.57 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.980s 47.478us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.150s 22.605us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.810s 21.266us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.640s 156.636us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.870s 9.830us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.240s 30.937us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.810s 21.266us 1 1 100.00
clkmgr_csr_aliasing 0.870s 9.830us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.800s 14.632us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.040s 41.844us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.950s 45.971us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.980s 47.478us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.650s 6.107us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.780s 3.333us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.650s 6.107us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.060s 52.287us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.780s 118.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.910s 65.860us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.910s 65.860us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.150s 22.605us 1 1 100.00
clkmgr_csr_rw 0.810s 21.266us 1 1 100.00
clkmgr_csr_aliasing 0.870s 9.830us 0 1 0.00
clkmgr_same_csr_outstanding 1.070s 47.455us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.150s 22.605us 1 1 100.00
clkmgr_csr_rw 0.810s 21.266us 1 1 100.00
clkmgr_csr_aliasing 0.870s 9.830us 0 1 0.00
clkmgr_same_csr_outstanding 1.070s 47.455us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 82.130s 10202.072us 0 1 0.00
clkmgr_tl_intg_err 0.630s 4.168us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.020s 54.819us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.020s 54.819us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.020s 54.819us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.020s 54.819us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.990s 39.171us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.630s 4.168us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.650s 6.107us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.780s 3.333us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.020s 54.819us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.160s 35.582us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.810s 21.266us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 82.130s 10202.072us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.810s 21.266us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.810s 21.266us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 82.130s 10202.072us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.880s 24.764us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.700s 9.584us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 43948921605952202753046477155790427901027268574921144046592605940616372249704 75
UVM_INFO @ 6106998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 51840624005143151844953615706250487467869828287135157564446250856081029616712 76
UVM_INFO @ 52287069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 53158671881411312211542840733156672130197690138633002029862093098541893854648 78
UVM_INFO @ 3333370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 58389876252476612631482607443071832630515550969409717109446852060291665304679 79
UVM_INFO @ 9583870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 99853131925041120485134580533540677018374631788468563678371704304635873203134 75
UVM_INFO @ 39170786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 26241311178851819920778351017094559790713692513874085994049777638596935845922 78
UVM_INFO @ 4167651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_csr_aliasing 24012074597655122751019403633811965720146586409909715842873885773754877314892 75
UVM_INFO @ 9829786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 1545263992725025072784209781131508389107381920918094988846431280401065009598 82
UVM_INFO @ 30936608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en 1 test run
clkmgr_regwen 36450245585420600717419897753587169207594361932420357599264766207915219288385 74
UVM_INFO @ 24764048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault 1 test run
clkmgr_sec_cm 92253667238875360781694577504166513168364757489411507425395418836784309166494 145
UVM_INFO @ 10202072331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 45520376226763607738492556250480266118921036850798722351793950204860404252019 75
UVM_INFO @ 156635787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 77876038800511859874021444111977219325129784871529749635854115351366123069295 75
UVM_INFO @ 47454921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---