Simulation Results: csrng

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.44 %
  • code
  • 90.19 %
  • assert
  • 90.61 %
  • func
  • 48.53 %
  • block
  • 95.10 %
  • line
  • 95.77 %
  • branch
  • 88.21 %
  • toggle
  • 91.08 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
83.33%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 23.829us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 40.434us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 13.227us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 10.000s 366.712us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 72.461us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 28.484us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 13.227us 1 1 100.00
csrng_csr_aliasing 4.000s 72.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 172.471us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 170.174us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 170.174us 0 1 0.00
stress_all 0 1 0.00
csrng_stress_all 5.000s 102.386us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 26.596us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 21.999us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 123.938us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 123.938us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 40.434us 1 1 100.00
csrng_csr_rw 2.000s 13.227us 1 1 100.00
csrng_csr_aliasing 4.000s 72.461us 1 1 100.00
csrng_same_csr_outstanding 2.000s 42.854us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 40.434us 1 1 100.00
csrng_csr_rw 2.000s 13.227us 1 1 100.00
csrng_csr_aliasing 4.000s 72.461us 1 1 100.00
csrng_same_csr_outstanding 2.000s 42.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
csrng_tl_intg_err 4.000s 236.510us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 45.630us 1 1 100.00
csrng_csr_rw 2.000s 13.227us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 172.471us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 5.000s 102.386us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 172.471us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 5.000s 102.386us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 172.471us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 236.510us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
csrng_sec_cm 4.000s 251.186us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 7.000s 382.507us 1 1 100.00
csrng_err 2.000s 25.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.149s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 93602827970382923514009721427475615681609235922414599203180142966397965448051 140
UVM_INFO @ 170173851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all 806145861717971952860760811710188858045083857566068023886015110488545011764 142
UVM_INFO @ 102385885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 49923787876290801905888212325402479508503128287196848020985946295651414545511 None