Simulation Results: edn/edn0

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 78.29 %
  • code
  • 88.13 %
  • assert
  • 96.24 %
  • func
  • 50.49 %
  • block
  • 95.38 %
  • line
  • 97.76 %
  • branch
  • 89.94 %
  • toggle
  • 74.91 %
  • FSM
  • 89.92 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 105.579us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 71.953us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 14.511us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 58.274us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 48.533us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 35.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 14.511us 1 1 100.00
edn_csr_aliasing 2.000s 48.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 103.736us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 103.736us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 103.736us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 26.935us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 25.412us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 19.317us 1 1 100.00
disable 1 2 50.00
edn_disable 2.000s 44.182us 1 1 100.00
edn_disable_auto_req_mode 1.000s 101.750us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 6.000s 447.503us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 15.648us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 22.097us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 268.582us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 268.582us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 71.953us 1 1 100.00
edn_csr_rw 1.000s 14.511us 1 1 100.00
edn_csr_aliasing 2.000s 48.533us 1 1 100.00
edn_same_csr_outstanding 2.000s 18.857us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 71.953us 1 1 100.00
edn_csr_rw 1.000s 14.511us 1 1 100.00
edn_csr_aliasing 2.000s 48.533us 1 1 100.00
edn_same_csr_outstanding 2.000s 18.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 599.671us 1 1 100.00
edn_tl_intg_err 2.000s 54.552us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 47.589us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 25.412us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 599.671us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 599.671us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 599.671us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 599.671us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 25.412us 1 1 100.00
edn_sec_cm 7.000s 599.671us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 25.412us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 54.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 22.000s 25135.417us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *. 1 test run
edn_disable_auto_req_mode 17973934856957048088919120645801534631386818423207947491065136184390195190860 103
UVM_INFO @ 101750307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---