Simulation Results: edn/edn1

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.07 %
  • code
  • 84.45 %
  • assert
  • 97.14 %
  • func
  • 79.62 %
  • line
  • 98.41 %
  • branch
  • 94.16 %
  • cond
  • 88.46 %
  • toggle
  • 95.76 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 46.609us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 18.307us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.890s 168.404us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.580s 36.611us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.270s 42.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 56.619us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.890s 168.404us 1 1 100.00
edn_csr_aliasing 1.270s 42.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.740s 118.929us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.740s 118.929us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.740s 118.929us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 27.804us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 66.386us 1 1 100.00
errs 1 1 100.00
edn_err 0.820s 67.519us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 37.477us 1 1 100.00
edn_disable_auto_req_mode 0.920s 62.983us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.920s 94.927us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.690s 12.155us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.840s 55.399us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.730s 111.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.730s 111.391us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.740s 18.307us 1 1 100.00
edn_csr_rw 0.890s 168.404us 1 1 100.00
edn_csr_aliasing 1.270s 42.478us 1 1 100.00
edn_same_csr_outstanding 1.280s 79.492us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.740s 18.307us 1 1 100.00
edn_csr_rw 0.890s 168.404us 1 1 100.00
edn_csr_aliasing 1.270s 42.478us 1 1 100.00
edn_same_csr_outstanding 1.280s 79.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.160s 406.240us 1 1 100.00
edn_tl_intg_err 3.310s 537.125us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 151.472us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 66.386us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.160s 406.240us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.160s 406.240us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.160s 406.240us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.160s 406.240us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 66.386us 1 1 100.00
edn_sec_cm 4.160s 406.240us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 66.386us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.310s 537.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 16.000s 1037.321us 1 1 100.00