Simulation Results: entropy_src/rng_16bits

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 65.12 %
  • code
  • 81.00 %
  • assert
  • 72.94 %
  • func
  • 41.43 %
  • block
  • 94.02 %
  • line
  • 97.73 %
  • branch
  • 85.86 %
  • toggle
  • 50.85 %
  • FSM
  • 89.58 %
Validation stages
V1
83.33%
V2
93.75%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 76.164us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 41.372us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 52.771us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 81.195us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 103.513us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 41.785us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 52.771us 1 1 100.00
entropy_src_csr_aliasing 4.000s 103.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 76.164us 1 1 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
entropy_src_fw_ov 102.000s 14066.200us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 102.000s 14066.200us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
rng_max_rate 0 1 0.00
entropy_src_rng_max_rate 440.000s 13121.702us 0 1 0.00
health_checks 1 1 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
entropy_src_intr 2.000s 133.974us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
entropy_src_functional_alerts 5.000s 693.253us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 65.000s 14507.830us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 54.059us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 9.000s 166.206us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 24.852us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 18.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 72.315us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 72.315us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 41.372us 1 1 100.00
entropy_src_csr_rw 2.000s 52.771us 1 1 100.00
entropy_src_csr_aliasing 4.000s 103.513us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 200.013us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 41.372us 1 1 100.00
entropy_src_csr_rw 2.000s 52.771us 1 1 100.00
entropy_src_csr_aliasing 4.000s 103.513us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 200.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 60.427us 1 1 100.00
entropy_src_tl_intg_err 3.000s 631.271us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
entropy_src_cfg_regwen 2.000s 16.861us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
entropy_src_fw_ov 102.000s 14066.200us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 54.059us 1 1 100.00
entropy_src_sec_cm 3.000s 60.427us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 54.059us 1 1 100.00
entropy_src_sec_cm 3.000s 60.427us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 68.000s 14187.276us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 54.059us 1 1 100.00
entropy_src_sec_cm 3.000s 60.427us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 54.059us 1 1 100.00
entropy_src_sec_cm 3.000s 60.427us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 54.059us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 693.253us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 631.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 88.000s 13149.108us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* 1 test run
entropy_src_rng_max_rate 99564606249588587901567260521939758130516096461380610574222744801874619520957 2384
UVM_INFO @ 13121702317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror extht_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 97604734679398705883743500319956125662163229859918700994598349951313225841946 113
UVM_INFO @ 41784675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---