Simulation Results: hmac

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.43 %
  • code
  • 96.00 %
  • assert
  • 95.86 %
  • func
  • 28.42 %
  • block
  • 97.55 %
  • line
  • 98.35 %
  • branch
  • 93.88 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.000s 611.781us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 30.009us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 28.622us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 17454.689us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.000s 369.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 178.000s 16694.449us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 28.622us 1 1 100.00
hmac_csr_aliasing 4.000s 369.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 20.000s 458.360us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 21.000s 815.322us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 168.000s 5223.743us 1 1 100.00
hmac_test_sha384_vectors 22.000s 223.515us 1 1 100.00
hmac_test_sha512_vectors 22.000s 784.775us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 214.365us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 688.638us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 365.925us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 18.000s 430.337us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 124.000s 2984.167us 1 1 100.00
error 1 1 100.00
hmac_error 66.000s 1772.416us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 43.000s 2041.152us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.000s 611.781us 1 1 100.00
hmac_long_msg 20.000s 458.360us 1 1 100.00
hmac_back_pressure 21.000s 815.322us 1 1 100.00
hmac_datapath_stress 124.000s 2984.167us 1 1 100.00
hmac_burst_wr 18.000s 430.337us 1 1 100.00
hmac_stress_all 189.000s 4992.723us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.000s 611.781us 1 1 100.00
hmac_long_msg 20.000s 458.360us 1 1 100.00
hmac_back_pressure 21.000s 815.322us 1 1 100.00
hmac_datapath_stress 124.000s 2984.167us 1 1 100.00
hmac_wipe_secret 43.000s 2041.152us 1 1 100.00
hmac_test_sha256_vectors 168.000s 5223.743us 1 1 100.00
hmac_test_sha384_vectors 22.000s 223.515us 1 1 100.00
hmac_test_sha512_vectors 22.000s 784.775us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 214.365us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 688.638us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 365.925us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.000s 611.781us 1 1 100.00
hmac_long_msg 20.000s 458.360us 1 1 100.00
hmac_back_pressure 21.000s 815.322us 1 1 100.00
hmac_datapath_stress 124.000s 2984.167us 1 1 100.00
hmac_burst_wr 18.000s 430.337us 1 1 100.00
hmac_error 66.000s 1772.416us 1 1 100.00
hmac_wipe_secret 43.000s 2041.152us 1 1 100.00
hmac_test_sha256_vectors 168.000s 5223.743us 1 1 100.00
hmac_test_sha384_vectors 22.000s 223.515us 1 1 100.00
hmac_test_sha512_vectors 22.000s 784.775us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 214.365us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 688.638us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 365.925us 1 1 100.00
hmac_stress_all 189.000s 4992.723us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 189.000s 4992.723us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 12.547us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 41.833us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 104.573us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 104.573us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 30.009us 1 1 100.00
hmac_csr_rw 1.000s 28.622us 1 1 100.00
hmac_csr_aliasing 4.000s 369.918us 1 1 100.00
hmac_same_csr_outstanding 1.000s 24.250us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 30.009us 1 1 100.00
hmac_csr_rw 1.000s 28.622us 1 1 100.00
hmac_csr_aliasing 4.000s 369.918us 1 1 100.00
hmac_same_csr_outstanding 1.000s 24.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 284.295us 1 1 100.00
hmac_tl_intg_err 2.000s 98.582us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 98.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.000s 611.781us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 577.565us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 77.000s 113762.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 126.449us 1 1 100.00