Simulation Results

Simulation Results: i2c

13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.71 %

code
89.21 %

assert
96.19 %

func
80.72 %

block
95.90 %

line
95.29 %

branch
92.63 %

toggle
86.90 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	179.000s	3810.650us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	26.000s	1821.858us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	34.763us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	22.857us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.000s	218.558us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	500.597us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	27.220us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	22.857us	1	1	100.00
	i2c_csr_aliasing	3.000s	500.597us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	24.638us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	308.000s	18572.757us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	43.000s	18746.663us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	53.791us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	2667.000s	3488.884us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	878.000s	3687.178us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.000s	55.419us	1	1	100.00
	i2c_host_fifo_fmt_empty	8.000s	307.929us	1	1	100.00
	i2c_host_fifo_reset_rx	6.000s	497.962us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	102.000s	2726.713us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1176.238us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	4.000s	110.416us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	6.000s	1011.263us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	7.000s	18814.567us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	8.000s	957.948us	1	1	100.00
	i2c_target_intr_smoke	6.000s	1181.246us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	773.717us	1	1	100.00
	i2c_target_fifo_reset_tx	4.000s	304.710us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	8.000s	957.948us	1	1	100.00
	i2c_target_intr_stress_wr	1635.000s	17088.700us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	12.000s	1622.302us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	13.000s	1837.374us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	7.000s	3135.748us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	4.000s	309.930us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	451.325us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	150.554us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	43.000s	18746.663us	1	1	100.00
	i2c_host_perf_precise	1.000s	60.042us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1176.238us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.000s	74.658us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	474.587us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	3305.658us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	292.812us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	15.000s	810.566us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	526.241us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	18.234us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	18.915us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	65.481us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	65.481us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	34.763us	1	1	100.00
	i2c_csr_rw	1.000s	22.857us	1	1	100.00
	i2c_csr_aliasing	3.000s	500.597us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	85.931us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	34.763us	1	1	100.00
	i2c_csr_rw	1.000s	22.857us	1	1	100.00
	i2c_csr_aliasing	3.000s	500.597us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	85.931us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.000s	302.591us	1	1	100.00
	i2c_sec_cm	2.000s	39.376us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.000s	302.591us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.000s	3840.740us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	4042.223us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.000s	312.055us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				2 test runs
	i2c_target_stress_wr	64374438132544926653975851264715905158869620321487809816261405841403289636370	None
	i2c_target_stress_all	63504411330012775018200419540715099184905671709092625436085961818951086693195	None
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	109529097270468917167188484916760278309578448040457348195608422966181250223754	93	UVM_INFO @ 3840740012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	22971217749839661370968438953213627384905694891033175237712086447415342924606	93	UVM_INFO @ 312054711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	104597121092254055064524395141846960952251241100336829768163574206984965827747	97	UVM_INFO @ 24638273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.fmtfull (addr=, Comparison=CompareOpEq, exp_data=, call_count=1438)				1 test run
	i2c_host_stress_all	94617485390469267070523574875276169699004864401537933178903066090523775607355	163	UVM_INFO @ 18572757491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	96748734066810148137760652062067165748436107988373304699632218844894762731360	93	UVM_INFO @ 1011263115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	90979187773214768399636879565147473895208300782998835644773245371021369252569	87	UVM_INFO @ 4042223252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	44576823418330594558911160972169857373131664203970013538787378420740798166532	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------