Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.54 %
  • code
  • 92.99 %
  • assert
  • 95.97 %
  • func
  • 85.67 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 88.06 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 639.935us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 65.033us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 58.916us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 80.989us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 85.324us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 153.302us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 58.916us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 85.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 373.310us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 561.095us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.543us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 5.000s 437.959us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 562.685us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_prog_failure 5.000s 437.959us 1 1 100.00
lc_ctrl_errors 4.000s 562.685us 1 1 100.00
lc_ctrl_security_escalation 6.000s 435.547us 1 1 100.00
lc_ctrl_jtag_state_failure 27.000s 2899.890us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.000s 2026.436us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 18788.690us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.000s 144.462us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.000s 3145.862us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.000s 2026.436us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 18788.690us 1 1 100.00
lc_ctrl_jtag_access 7.000s 431.905us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 1087.960us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 388.745us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 532.865us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 3924.003us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 1641.858us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 43.686us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 302.552us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 384.276us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 181.337us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 16.132us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.000s 3197.462us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 27.921us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 113.647us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 113.647us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 65.033us 1 1 100.00
lc_ctrl_csr_rw 2.000s 58.916us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 85.324us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 78.220us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 65.033us 1 1 100.00
lc_ctrl_csr_rw 2.000s 58.916us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 85.324us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 78.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 62.095us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 62.095us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 561.095us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 151.733us 1 1 100.00
lc_ctrl_sec_cm 3.000s 297.168us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 435.547us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 373.310us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.000s 3145.862us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 271.800us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 271.800us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 16.000s 2327.492us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.000s 1160.975us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.000s 1160.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 38.000s 5970.645us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 52226993335633736548934761283640885076298361797777744954908467180607953385131 2618
UVM_INFO @ 5970645176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---