Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.95 %
  • code
  • 93.57 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 97.02 %
  • line
  • 97.57 %
  • branch
  • 92.45 %
  • toggle
  • 89.03 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 30.995us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 18.443us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 233.188us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 40.201us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.451us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 34.318us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 233.188us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 50.809us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 2947.997us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.661us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 120.437us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 615.605us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_prog_failure 2.000s 120.437us 1 1 100.00
lc_ctrl_errors 5.000s 615.605us 1 1 100.00
lc_ctrl_security_escalation 10.000s 449.746us 1 1 100.00
lc_ctrl_jtag_state_failure 14.000s 6249.516us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.000s 835.641us 1 1 100.00
lc_ctrl_jtag_errors 21.000s 3487.913us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 207.322us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.000s 597.057us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.000s 835.641us 1 1 100.00
lc_ctrl_jtag_errors 21.000s 3487.913us 1 1 100.00
lc_ctrl_jtag_access 8.000s 546.980us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 6921.775us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 224.392us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 90.386us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 1350.335us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 1728.624us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 98.215us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 97.202us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 118.839us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 4481.275us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 71.261us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 27.000s 9555.411us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 16.010us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 84.075us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 84.075us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 18.443us 1 1 100.00
lc_ctrl_csr_rw 2.000s 233.188us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.451us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 21.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 18.443us 1 1 100.00
lc_ctrl_csr_rw 2.000s 233.188us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 24.451us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 21.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 65.147us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 65.147us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 2947.997us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 858.433us 1 1 100.00
lc_ctrl_sec_cm 3.000s 860.363us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 10.000s 449.746us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 50.809us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.000s 597.057us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 323.595us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 323.595us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 420.436us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 760.889us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 760.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 30.000s 8028.247us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 64235150908811372967822172113281727149773733983752682416683171044602795352130 608
UVM_INFO @ 8028246672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---