Simulation Results: mbx

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.51 %
  • code
  • 89.61 %
  • assert
  • 96.86 %
  • func
  • 76.07 %
  • block
  • 95.61 %
  • line
  • 95.13 %
  • branch
  • 88.29 %
  • toggle
  • 85.41 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 54.000s 10333.172us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 27.487us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 14.025us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 930.116us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 56.612us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 5.541us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 14.025us 1 1 100.00
mbx_csr_aliasing 1.000s 56.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 8.000s 724.028us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 143.588us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 69.000s 3890.754us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 10.000s 3006.424us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 16.470us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 14.485us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 13.850us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 13.850us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 27.487us 1 1 100.00
mbx_csr_rw 1.000s 14.025us 1 1 100.00
mbx_csr_aliasing 1.000s 56.612us 1 1 100.00
mbx_same_csr_outstanding 1.000s 17.430us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 27.487us 1 1 100.00
mbx_csr_rw 1.000s 14.025us 1 1 100.00
mbx_csr_aliasing 1.000s 56.612us 1 1 100.00
mbx_same_csr_outstanding 1.000s 17.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 85.218us 1 1 100.00
mbx_sec_cm 1.000s 16.333us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 41771505595266109199227328504614684167868390819304099558681119865095299570368 85
TL item was: req: (cip_tl_seq_item@18541) { a_addr: 'h6ed26914 a_data: 'h21c4be56 a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'h6d a_opcode: 'h1 a_user: 'h257d6 d_param: 'h0 d_source: 'h6d d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 13850326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 22283696723041353432569665859979698637834258438592772300047350055128909926236 86
TL item was: req: (cip_tl_seq_item@20937) { a_addr: 'h595b4330 a_data: 'had21b0cf a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'h2b a_opcode: 'h1 a_user: 'h26637 d_param: 'h0 d_source: 'h2b d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 5541103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress 10615300198926629702636998628502953692739515303430252267349468338620432128473 453
UVM_INFO @ 724028290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress_zero_delays 4157902614043939848408508228783759512632526098414644224770526229443948413526 410
UVM_INFO @ 143588174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---