Simulation Results: otp_ctrl

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.75 %
  • code
  • 72.79 %
  • assert
  • 92.80 %
  • func
  • 58.67 %
  • line
  • 87.55 %
  • branch
  • 84.45 %
  • cond
  • 87.19 %
  • toggle
  • 67.29 %
  • FSM
  • 37.49 %
Validation stages
V1
100.00%
V2
70.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.630s 58.881us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.160s 241.831us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.810s 117.420us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.990s 215.459us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.730s 473.312us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.910s 871.716us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.490s 161.668us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.990s 215.459us 1 1 100.00
otp_ctrl_csr_aliasing 8.910s 871.716us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.370s 49.427us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.370s 43.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 99.320s 19453.102us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.770s 312.252us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 9.500s 476.235us 1 1 100.00
otp_ctrl_check_fail 2.710s 111.241us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.780s 162.743us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.880s 1221.014us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 36.250s 1972.665us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 7.810s 694.647us 0 1 0.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 3.470s 71.586us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 7.190s 4904.572us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 12.660s 851.531us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 22.290s 7051.024us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.820s 87.539us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.570s 802.240us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.810s 78.625us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.810s 78.625us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.810s 117.420us 1 1 100.00
otp_ctrl_csr_rw 1.990s 215.459us 1 1 100.00
otp_ctrl_csr_aliasing 8.910s 871.716us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.550s 1348.389us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.810s 117.420us 1 1 100.00
otp_ctrl_csr_rw 1.990s 215.459us 1 1 100.00
otp_ctrl_csr_aliasing 8.910s 871.716us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.550s 1348.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
otp_ctrl_tl_intg_err 22.510s 2778.983us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 22.510s 2778.983us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.160s 241.831us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.160s 241.831us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
otp_ctrl_macro_errs 7.190s 4904.572us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
otp_ctrl_macro_errs 7.190s 4904.572us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 21.540s 1055.178us 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.770s 312.252us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.710s 111.241us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.880s 1221.014us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.880s 1221.014us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.880s 1221.014us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.880s 1221.014us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.880s 1221.014us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.160s 241.831us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.880s 1221.014us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.160s 241.831us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 268.690s 23221.198us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.780s 162.743us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.160s 241.831us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.160s 241.831us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 7.190s 4904.572us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 68.830s 46526.078us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 70.800s 3272.736us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_dai_errs 50762427727090632231881952962161254491668102320307115847764406143643952980793 3026
UVM_INFO @ 71585772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 16484365021220502654863740053200345497395656242359141220001911517605818507606 3545
UVM_INFO @ 4904571569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 33323864393215332375795203312076843655919814713185367669039908256708451548143 120869
UVM_INFO @ 19453101646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 97390246873808527841998244124437136200852628820743315390962223502937795428182 89
UVM_INFO @ 46526078120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_parallel_lc_req 46944108316371946090186425319678402487016085044831402094625890078422883711550 6706
UVM_INFO @ 694646889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 82658001548574526905980767128558477897640034102767274606964882407818578926538 1418
UVM_INFO @ 111240665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all 73862325443848417143311180108133909027775381826334474417382204704107915985966 21171
UVM_INFO @ 7051024351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---