Simulation Results: rom_ctrl/32kb

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.75 %
  • code
  • 93.74 %
  • assert
  • 96.79 %
  • func
  • 84.71 %
  • block
  • 95.10 %
  • line
  • 94.99 %
  • branch
  • 93.28 %
  • toggle
  • 86.68 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 319.412us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 595.719us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.000s 290.934us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 177.842us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 289.913us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 395.661us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.000s 290.934us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 289.913us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 128.454us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 833.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.000s 588.916us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.000s 832.402us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 383.533us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.000s 2760.457us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 675.792us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 675.792us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 595.719us 1 1 100.00
rom_ctrl_csr_rw 4.000s 290.934us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 289.913us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 388.002us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 595.719us 1 1 100.00
rom_ctrl_csr_rw 4.000s 290.934us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 289.913us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 388.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.000s 828.395us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 96.000s 595.281us 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 1341.646us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 96.000s 595.281us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 96.000s 595.281us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.000s 595.281us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 96.000s 595.281us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 319.412us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 319.412us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 319.412us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 1341.646us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 383.533us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.000s 15291.464us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.000s 828.395us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.000s 595.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 9.000s 1494.713us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 113543698435796301619567817750169845516946156775708109552650292997637718900033 91
UVM_INFO @ 1494712615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---