Simulation Results: rom_ctrl/64kb

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 91.75 %
  • assert
  • 96.79 %
  • func
  • 97.88 %
  • block
  • 95.91 %
  • line
  • 96.44 %
  • branch
  • 93.01 %
  • toggle
  • 87.07 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 222.622us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 537.279us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.000s 16500.421us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 1028.845us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 369.861us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 741.502us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.000s 16500.421us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 369.861us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 3694.571us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.000s 300.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.000s 565.173us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.000s 1122.812us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 2107.482us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.000s 3331.498us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 249.381us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 249.381us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 537.279us 1 1 100.00
rom_ctrl_csr_rw 6.000s 16500.421us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 369.861us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 372.961us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 537.279us 1 1 100.00
rom_ctrl_csr_rw 6.000s 16500.421us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 369.861us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 372.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.000s 4168.765us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 99.000s 415.052us 1 1 100.00
rom_ctrl_tl_intg_err 42.000s 530.988us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 99.000s 415.052us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 99.000s 415.052us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 99.000s 415.052us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 99.000s 415.052us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 222.622us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 222.622us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 222.622us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.000s 530.988us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 2107.482us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.000s 10012.193us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.000s 4168.765us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 99.000s 415.052us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 68.000s 12906.391us 1 1 100.00