Simulation Results: rstmgr

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.10 %
  • code
  • 99.29 %
  • assert
  • 97.44 %
  • func
  • 94.58 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.100s 58.596us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.340s 95.437us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.930s 37.542us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.090s 196.378us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.160s 40.466us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.190s 67.167us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.930s 37.542us 1 1 100.00
rstmgr_csr_aliasing 1.160s 40.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.450s 188.474us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.990s 40.710us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.910s 63.014us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.100s 646.379us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.100s 646.379us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.100s 646.379us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.100s 646.379us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.740s 158.349us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.120s 40.297us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.370s 41.728us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.370s 41.728us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.340s 95.437us 1 1 100.00
rstmgr_csr_rw 0.930s 37.542us 1 1 100.00
rstmgr_csr_aliasing 1.160s 40.466us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 37.454us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.340s 95.437us 1 1 100.00
rstmgr_csr_rw 0.930s 37.542us 1 1 100.00
rstmgr_csr_aliasing 1.160s 40.466us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 37.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 28.600s 6917.143us 1 1 100.00
rstmgr_tl_intg_err 3.680s 379.967us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 28.600s 6917.143us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 28.600s 6917.143us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.680s 379.967us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.210s 63.898us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.470s 445.420us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.050s 291.390us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 28.600s 6917.143us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.930s 37.542us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.930s 37.542us 1 1 100.00