Simulation Results

Simulation Results: rv_dm/use_dmi_interface

13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.37 %

code
75.01 %

assert
96.20 %

func
90.91 %

block
90.02 %

line
89.88 %

branch
72.94 %

toggle
74.71 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	689.312us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	296.498us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	32.000s	132.346us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	35.000s	3187.479us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	32.000s	987.263us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	33.000s	5232.210us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	31.000s	1455.228us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	129.000s	67418.192us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	184.000s	197690.832us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	241.015us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	197.138us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	491.516us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	31.000s	212.315us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	32.000s	132.084us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	33.000s	348.725us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	33.000s	249.277us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	30.000s	285.294us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	241.015us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	204.521us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	372.714us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	491.516us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	31.000s	82.225us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	31.000s	255.206us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	76.382us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	51.000s	7366.347us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	45.000s	2183.217us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	32.000s	454.414us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	45.000s	2183.217us	1	1	100.00
	rv_dm_csr_rw	31.000s	76.382us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	148.043us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	61.415us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	689.312us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	31.000s	163.196us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	618.681us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	30.000s	128.986us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	31.000s	1444.228us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	33.000s	1103.950us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	141.963us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	31.000s	1678.912us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	32.000s	44.984us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	32.000s	493.071us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	38.000s	5619.517us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	33.000s	282.788us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	32.000s	155.801us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	53.000s	10339.994us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	61.000s	3586.242us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	227.870us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	10803.000s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	29.000s	176.292us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	529.018us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	529.018us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	45.000s	2183.217us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	255.206us	1	1	100.00
	rv_dm_csr_rw	31.000s	76.382us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	1039.720us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	45.000s	2183.217us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	255.206us	1	1	100.00
	rv_dm_csr_rw	31.000s	76.382us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	1039.720us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	35.000s	807.264us	1	1	100.00
	rv_dm_tl_intg_err	47.000s	6276.649us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	47.000s	6276.649us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	38.000s	5619.517us	1	1	100.00
	rv_dm_debug_disabled	30.000s	132.254us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	38.000s	5619.517us	1	1	100.00
	rv_dm_debug_disabled	30.000s	132.254us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	689.312us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	30.000s	162.829us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	32.000s	72.526us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	32.000s	72.526us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	30.000s	162.829us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	30.000s	256.903us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	181.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	2925924351694813517205370062651222842779408335310083910503781781158081279749	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24244
	rv_dm_bad_sba_tl_access	66842881371533758169620106627211318711815204080563975481749162537736507386153	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24270
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	59176063284760789938860506080336548224685603889774188914301102258313843370866	107	UVM_INFO @ 141963414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	46030397856174046167025688307566178350554051086555892059316619002738039837139	107	UVM_INFO @ 44984483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	79026646203782703510953000858143433119402065281500754492633414768061625639580	87	UVM_INFO @ 155800610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	12320292088672369649444743009312733986003460515605852524031054447527548720053	93	UVM_INFO @ 256902866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	114390075726994947185775377709918014781682294432516976236887615136129165021480	87	UVM_INFO @ 212315018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	98137153825914482467885641547307263030119863769792916214766195199463091270636	87	UVM_INFO @ 493071377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	112526422841764062609702783265752924585270309424874145033989825634940439044170	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	49610990066440981043781427116293088136280683426243806869341262255554401298577	None