Simulation Results: rv_timer

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 86.679us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 50.759us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 51.467us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 61.720us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 61.244us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 17.641us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 51.467us 1 1 100.00
rv_timer_csr_aliasing 1.000s 61.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 1.000s 329.180us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 2347.379us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 282.000s 908888.852us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 282.000s 908888.852us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 2328.745us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 12.953us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 13.960us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 99.127us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 99.127us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 50.759us 1 1 100.00
rv_timer_csr_rw 1.000s 51.467us 1 1 100.00
rv_timer_csr_aliasing 1.000s 61.244us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 60.741us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 50.759us 1 1 100.00
rv_timer_csr_rw 1.000s 51.467us 1 1 100.00
rv_timer_csr_aliasing 1.000s 61.244us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 60.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 251.621us 1 1 100.00
rv_timer_tl_intg_err 2.000s 447.665us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 447.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 223.019us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 158.453us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 37.000s 5283.141us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 47951791502141108775278011828186683447008619976529744508460617829447743520175 84
UVM_INFO @ 223018847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 53388818206160763880241808751277404409555239674434682700791474220944787609430 84
UVM_INFO @ 158452674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---