Simulation Results: spi_device/1r1w

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.81 %
  • code
  • 91.63 %
  • assert
  • 94.64 %
  • func
  • 68.17 %
  • block
  • 98.32 %
  • line
  • 98.75 %
  • branch
  • 96.95 %
  • toggle
  • 81.25 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 77.000s 6632.799us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 123.782us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 611.594us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 40.000s 5503.546us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.000s 409.419us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 31.575us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 611.594us 1 1 100.00
spi_device_csr_aliasing 11.000s 409.419us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 13.996us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 251.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 122.975us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 2.095us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 3.512us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 299.248us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 299.248us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.000s 149.680us 1 1 100.00
spi_device_tpm_sts_read 2.000s 32.029us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 39.000s 10352.905us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.000s 70.780us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 847.424us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 847.424us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 10.000s 912.146us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 10.000s 912.146us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 10.000s 912.146us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 10.000s 912.146us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 10.000s 912.146us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.000s 501.717us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 4.000s 34.173us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 4.000s 34.173us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 4.000s 34.173us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 16.000s 841.237us 1 1 100.00
spi_device_read_buffer_direct 18.000s 6101.428us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 4.000s 34.173us 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 97.000s 8627.223us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 6.000s 327.182us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 6.000s 327.182us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 77.000s 6632.799us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 100.000s 33930.841us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 591.000s 67269.907us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 44.953us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 16.851us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 115.461us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 115.461us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 123.782us 1 1 100.00
spi_device_csr_rw 3.000s 611.594us 1 1 100.00
spi_device_csr_aliasing 11.000s 409.419us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 420.299us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 123.782us 1 1 100.00
spi_device_csr_rw 3.000s 611.594us 1 1 100.00
spi_device_csr_aliasing 11.000s 409.419us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 420.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 272.498us 1 1 100.00
spi_device_tl_intg_err 16.000s 299.006us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 16.000s 299.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 37.000s 7801.763us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 46626359348170325100653775542185765978257957496308686437573991872609682247878 87
UVM_ERROR @ 1291104 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[989] not found within the scope .
UVM_ERROR @ 1291104 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[989] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 53517457608031537091657700087703954423741021467452891658273513052003635351439 85
UVM_ERROR @ 869214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3c9e4e [1111001001111001001110] vs 0x0 [0])
UVM_ERROR @ 954214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ab096 [1010101011000010010110] vs 0x0 [0])
UVM_ERROR @ 984214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcb8ad4 [110010111000101011010100] vs 0x0 [0])
UVM_ERROR @ 1070214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe5de66 [111001011101111001100110] vs 0x0 [0])