Simulation Results: sram_ctrl/main

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.71 %
  • code
  • 96.28 %
  • assert
  • 96.46 %
  • func
  • 91.40 %
  • block
  • 95.27 %
  • line
  • 95.92 %
  • branch
  • 92.71 %
  • toggle
  • 96.49 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 1959.011us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 18.558us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.250us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 181.721us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.120us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 713.911us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.250us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.120us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 205.000s 28233.551us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 44.000s 2880.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 27.000s 6119.745us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 81.000s 10073.811us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 112.000s 22740.466us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 46.000s 37199.754us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 19.000s 19923.056us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 752.607us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 695.711us 1 1 100.00
sram_ctrl_partial_access_b2b 221.000s 86149.903us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 8.000s 13330.884us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 1588.159us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 1365.523us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 4071.978us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 774.191us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 263.000s 176563.347us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.999us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 247.491us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 247.491us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.558us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.250us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.120us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 52.452us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.558us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.250us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.120us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 52.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 12866.677us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 467.693us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 306.430us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 467.693us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 306.430us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 4071.978us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 4071.978us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.250us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 752.607us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 752.607us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 752.607us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 19.000s 19923.056us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 3021.153us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 12866.677us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2461.535us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1959.011us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1959.011us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 752.607us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 467.693us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 19.000s 19923.056us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 467.693us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 467.693us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 1959.011us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 467.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 20.000s 6433.517us 1 1 100.00