Simulation Results: sram_ctrl/ret

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.53 %
  • code
  • 83.36 %
  • assert
  • 96.43 %
  • func
  • 94.80 %
  • block
  • 93.80 %
  • line
  • 94.97 %
  • branch
  • 89.51 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 43.406us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 37.975us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.616us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 44.701us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 81.325us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 24.082us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 46.616us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 81.325us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 72.173us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 65.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 710.980us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 196.000s 15126.026us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 4.000s 217.170us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 297.525us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1597.526us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 1050.887us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 174.933us 1 1 100.00
sram_ctrl_partial_access_b2b 210.000s 69902.014us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 36.012us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 48.934us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 148.374us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 852.539us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 29.160us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 30.000s 12727.457us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 41.900us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 320.889us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 320.889us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 37.975us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.616us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 81.325us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 92.966us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 37.975us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.616us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 81.325us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 92.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 869.696us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 198.497us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 206.209us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 198.497us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 206.209us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 852.539us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 852.539us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.616us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1050.887us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1050.887us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1050.887us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1597.526us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 43.467us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 869.696us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 69.375us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 43.406us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 43.406us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 1050.887us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 198.497us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1597.526us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 198.497us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 198.497us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 43.406us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 198.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 2161.001us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 14333999061519454061428540231473014415860743682007020812183401279896420596539 88
UVM_INFO @ 24081536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---