Simulation Results: uart

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.45 %
  • code
  • 77.55 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.66 %
  • line
  • 99.24 %
  • branch
  • 97.42 %
  • toggle
  • 88.53 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 737.183us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 57.601us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 39.447us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 91.113us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 38.436us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 26.468us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 39.447us 1 1 100.00
uart_csr_aliasing 1.000s 38.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 42.000s 30713.603us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 737.183us 1 1 100.00
uart_tx_rx 42.000s 30713.603us 1 1 100.00
parity_error 2 2 100.00
uart_intr 30.000s 42210.815us 1 1 100.00
uart_rx_parity_err 25.000s 82291.551us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 42.000s 30713.603us 1 1 100.00
uart_intr 30.000s 42210.815us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 140.000s 197532.665us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 14.000s 96151.039us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 242.000s 202188.553us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 30.000s 42210.815us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 30.000s 42210.815us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 30.000s 42210.815us 1 1 100.00
perf 1 1 100.00
uart_perf 557.000s 21942.247us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.000s 3687.975us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.000s 3687.975us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 21.000s 16763.488us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 1786.559us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.000s 1100.829us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 15.000s 2840.844us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 181.000s 100764.140us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 129.000s 281978.717us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 36.398us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 14.327us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 271.022us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 271.022us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 57.601us 1 1 100.00
uart_csr_rw 1.000s 39.447us 1 1 100.00
uart_csr_aliasing 1.000s 38.436us 1 1 100.00
uart_same_csr_outstanding 1.000s 63.582us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 57.601us 1 1 100.00
uart_csr_rw 1.000s 39.447us 1 1 100.00
uart_csr_aliasing 1.000s 38.436us 1 1 100.00
uart_same_csr_outstanding 1.000s 63.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 71.096us 1 1 100.00
uart_tl_intg_err 2.000s 45.043us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 45.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.000s 875.612us 1 1 100.00