Simulation Results: ac_range_check

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.84 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.75 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 21.000s 439.299us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 42.000s 2235.898us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 66.405us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 345.423us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 32.000s 2825.315us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1412.590us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 124.146us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 345.423us 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1412.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 56.789us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 31.000s 1950.213us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 220.000s 49466.826us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 26.663us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 16.879us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 70.390us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 70.390us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 66.405us 1 1 100.00
ac_range_check_csr_rw 3.000s 345.423us 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1412.590us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 700.142us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 66.405us 1 1 100.00
ac_range_check_csr_rw 3.000s 345.423us 1 1 100.00
ac_range_check_csr_aliasing 15.000s 1412.590us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 700.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 408.138us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 408.138us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 408.138us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 408.138us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 57.000s 5983.599us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 37.401us 1 1 100.00
ac_range_check_tl_intg_err 6.000s 222.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 223.000s 635.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 26.000s 1376.909us 1 1 100.00