Simulation Results: aes/gcm_masked

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.13 %
  • code
  • 95.73 %
  • assert
  • 98.29 %
  • func
  • 70.37 %
  • block
  • 95.89 %
  • line
  • 97.53 %
  • branch
  • 90.00 %
  • toggle
  • 97.96 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 80.873us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 116.255us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 103.322us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 92.930us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 847.348us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 316.652us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 63.604us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 92.930us 1 1 100.00
aes_csr_aliasing 3.000s 316.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 116.255us 1 1 100.00
aes_config_error 4.000s 84.373us 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 116.255us 1 1 100.00
aes_config_error 4.000s 84.373us 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 150.593us 1 1 100.00
aes_b2b 12.000s 410.625us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 116.255us 1 1 100.00
aes_config_error 4.000s 84.373us 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
aes_alert_reset 5.000s 926.934us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 120.989us 1 1 100.00
aes_config_error 4.000s 84.373us 1 1 100.00
aes_alert_reset 5.000s 926.934us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 1080.682us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 299.662us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 9.000s 773.984us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 926.934us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 150.593us 1 1 100.00
aes_sideload 3.000s 87.833us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 6.000s 166.066us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 53.000s 1142.580us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 69.429us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 100.120us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 97.664us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 97.664us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 103.322us 1 1 100.00
aes_csr_rw 1.000s 92.930us 1 1 100.00
aes_csr_aliasing 3.000s 316.652us 1 1 100.00
aes_same_csr_outstanding 2.000s 114.051us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 103.322us 1 1 100.00
aes_csr_rw 1.000s 92.930us 1 1 100.00
aes_csr_aliasing 3.000s 316.652us 1 1 100.00
aes_same_csr_outstanding 2.000s 114.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 86.994us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 107.802us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 107.802us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 107.802us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 107.802us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 119.697us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 589.738us 1 1 100.00
aes_tl_intg_err 2.000s 111.460us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 111.460us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 926.934us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 107.802us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 107.802us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 116.255us 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
aes_alert_reset 5.000s 926.934us 1 1 100.00
aes_core_fi 59.000s 10005.480us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 3.000s 69.429us 1 1 100.00
aes_config_error 4.000s 84.373us 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
aes_core_fi 59.000s 10005.480us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 107.802us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 53.323us 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 150.593us 1 1 100.00
aes_sideload 3.000s 87.833us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 53.323us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 53.323us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 53.323us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 53.323us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 53.323us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 150.593us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 318.364us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
aes_ctr_fi 2.000s 49.098us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 318.364us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 318.364us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_ctr_fi 2.000s 49.098us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 318.364us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
aes_ctr_fi 2.000s 49.098us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 926.934us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
aes_ctr_fi 2.000s 49.098us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
aes_ctr_fi 2.000s 49.098us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_ctr_fi 2.000s 49.098us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_ghash_fi 3.000s 61.394us 1 1 100.00
aes_fi 4.000s 318.364us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 318.364us 1 1 100.00
aes_control_fi 2.000s 54.269us 1 1 100.00
aes_cipher_fi 32.000s 10032.625us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 33.000s 5574.400us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 68551330384866414083442686053242588989623176596369600627399353047202459850875 154
UVM_INFO @ 10032625453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 58676670171952655196746964310513012890091242830074916344622587774764929084112 146
UVM_INFO @ 10005479848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 38236561712667070898274935395166276992353489595226188260428544815374761175502 845
UVM_INFO @ 5574399895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---