Simulation Results: aes/gcm_unmasked

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.21 %
  • code
  • 90.57 %
  • assert
  • 97.94 %
  • func
  • 67.13 %
  • block
  • 90.56 %
  • line
  • 92.72 %
  • branch
  • 83.00 %
  • toggle
  • 97.90 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 182.159us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 66.561us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 58.398us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 62.110us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1380.598us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 282.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 65.798us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 62.110us 1 1 100.00
aes_csr_aliasing 2.000s 282.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 66.561us 1 1 100.00
aes_config_error 3.000s 63.631us 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 66.561us 1 1 100.00
aes_config_error 3.000s 63.631us 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 129.595us 1 1 100.00
aes_b2b 4.000s 114.560us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 66.561us 1 1 100.00
aes_config_error 3.000s 63.631us 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
aes_alert_reset 2.000s 200.973us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 67.329us 1 1 100.00
aes_config_error 3.000s 63.631us 1 1 100.00
aes_alert_reset 2.000s 200.973us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 217.187us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 184.912us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 200.973us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 129.595us 1 1 100.00
aes_sideload 2.000s 75.722us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 89.377us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 25.000s 2954.479us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 86.331us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 255.102us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 255.102us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 58.398us 1 1 100.00
aes_csr_rw 2.000s 62.110us 1 1 100.00
aes_csr_aliasing 2.000s 282.059us 1 1 100.00
aes_same_csr_outstanding 2.000s 135.737us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 58.398us 1 1 100.00
aes_csr_rw 2.000s 62.110us 1 1 100.00
aes_csr_aliasing 2.000s 282.059us 1 1 100.00
aes_same_csr_outstanding 2.000s 135.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 555.626us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 371.064us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 371.064us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 371.064us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 371.064us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 225.052us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 765.130us 1 1 100.00
aes_tl_intg_err 1.000s 262.025us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 262.025us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 200.973us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 371.064us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 371.064us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 66.561us 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
aes_alert_reset 2.000s 200.973us 1 1 100.00
aes_core_fi 2.000s 81.322us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 63.631us 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
aes_core_fi 2.000s 81.322us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 371.064us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 93.952us 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 129.595us 1 1 100.00
aes_sideload 2.000s 75.722us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 93.952us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 93.952us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 93.952us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 93.952us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 93.952us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 129.595us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 79.097us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
aes_ctr_fi 2.000s 56.636us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 79.097us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 79.097us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_ctr_fi 2.000s 56.636us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 79.097us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
aes_ctr_fi 2.000s 56.636us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 200.973us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
aes_ctr_fi 2.000s 56.636us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
aes_ctr_fi 2.000s 56.636us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_ctr_fi 2.000s 56.636us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 2.000s 79.097us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 79.097us 1 1 100.00
aes_control_fi 2.000s 52.631us 1 1 100.00
aes_cipher_fi 14.000s 10008.785us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 40.920us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 54056372779564120215996025660311180255697078269732859005853077090575031416502 146
UVM_INFO @ 10008784819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 107873017706149546682983357970801714222269918107379983437789048183628649466306 158
UVM_INFO @ 40920301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---