Simulation Results: clkmgr

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.42 %
  • code
  • 67.24 %
  • assert
  • 89.05 %
  • func
  • 60.98 %
  • line
  • 81.61 %
  • branch
  • 86.53 %
  • cond
  • 77.04 %
  • toggle
  • 91.04 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.840s 26.188us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.950s 26.447us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.610s 2.506us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.810s 6.179us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.240s 60.470us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.810s 12.266us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.610s 2.506us 0 1 0.00
clkmgr_csr_aliasing 1.240s 60.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.370s 84.768us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.960s 35.840us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.960s 46.574us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.840s 26.188us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 1.000s 52.307us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.640s 7.249us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 1.000s 52.307us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.080s 46.034us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.860s 18.368us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.740s 122.039us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.740s 122.039us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.950s 26.447us 1 1 100.00
clkmgr_csr_rw 0.610s 2.506us 0 1 0.00
clkmgr_csr_aliasing 1.240s 60.470us 1 1 100.00
clkmgr_same_csr_outstanding 0.740s 16.836us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.950s 26.447us 1 1 100.00
clkmgr_csr_rw 0.610s 2.506us 0 1 0.00
clkmgr_csr_aliasing 1.240s 60.470us 1 1 100.00
clkmgr_same_csr_outstanding 0.740s 16.836us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 89.210s 10044.212us 0 1 0.00
clkmgr_tl_intg_err 0.930s 16.212us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 49.094us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 49.094us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 49.094us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 49.094us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.640s 7.799us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.930s 16.212us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 1.000s 52.307us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.640s 7.249us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 49.094us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.970s 24.656us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.610s 2.506us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 89.210s 10044.212us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.610s 2.506us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.610s 2.506us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 89.210s 10044.212us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.650s 3.766us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.580s 108.074us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 2269394398410833623919968916243356680875703895872238541255682334611940056146 75
UVM_INFO @ 52307230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 53755506839584598979238148846672980902625891617758502723386464749528085290634 76
UVM_INFO @ 46033942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 24278537813176720661324260681438384529043721764809238320683336333788060967732 78
UVM_INFO @ 7248532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 21151321697410816253225164932134327792736686147658272447834491312174754477416 85
UVM_INFO @ 108073657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 62047113551338116895133720872515131090417613662160730189262244961160642820617 75
UVM_INFO @ 7799072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 23573239038025641409900286480228456254313940771304283969415081131213657864586 75
UVM_INFO @ 2506475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_tl_intg_err 22178060436325073078931119708360392978840994954901591539095003271795094435759 90
UVM_INFO @ 16211760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 58680533281167643152148533541112945188572470090672272768899087659026035390828 76
UVM_INFO @ 12265822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 52297476862336260142470461238397784989929419830121576387133989272592668004046 74
UVM_INFO @ 3765826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 73969242148863018562060706329061638504369879459005565621493723376699110144599 107
UVM_INFO @ 10044212192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 89032560713741342992306007615335164895477252480908123936837646044760501198141 75
UVM_INFO @ 6179109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 76531345943430079623438812898713962547789285673006189681859538532787254202346 75
UVM_INFO @ 16836444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---