Simulation Results: csrng

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.87 %
  • code
  • 89.10 %
  • assert
  • 92.79 %
  • func
  • 45.72 %
  • block
  • 95.25 %
  • line
  • 95.85 %
  • branch
  • 88.65 %
  • toggle
  • 86.21 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 26.490us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 25.909us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 49.173us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 13.000s 622.810us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 240.937us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 122.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 49.173us 1 1 100.00
csrng_csr_aliasing 5.000s 240.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 224.916us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 145.992us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 145.992us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 5.000s 64.829us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 50.905us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 1.000s 41.654us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 129.919us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 129.919us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 25.909us 1 1 100.00
csrng_csr_rw 3.000s 49.173us 1 1 100.00
csrng_csr_aliasing 5.000s 240.937us 1 1 100.00
csrng_same_csr_outstanding 2.000s 27.635us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 25.909us 1 1 100.00
csrng_csr_rw 3.000s 49.173us 1 1 100.00
csrng_csr_aliasing 5.000s 240.937us 1 1 100.00
csrng_same_csr_outstanding 2.000s 27.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
csrng_tl_intg_err 7.000s 485.634us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 13.811us 0 1 0.00
csrng_csr_rw 3.000s 49.173us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 224.916us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 5.000s 64.829us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 224.916us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 5.000s 64.829us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 224.916us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 7.000s 485.634us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
csrng_sec_cm 2.000s 82.447us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 94.272us 1 1 100.00
csrng_err 2.000s 48.660us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10800.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 96775872754354215826196442770102239712727444150693269595878644881790367521898 109
UVM_INFO @ 145992008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 7842906903424172611112828320563900658703171676334344037468092962977310516265 99
UVM_INFO @ 13810826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 36956364587903916581498591465152697215887825620391184283691214800246061986549 None