Simulation Results: dma

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.41 %
  • code
  • 91.50 %
  • assert
  • 96.61 %
  • func
  • 65.13 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 592.227us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 228.754us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 349.399us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 39.302us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 28.261us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 12.000s 7724.543us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 294.936us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 25.149us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 28.261us 1 1 100.00
dma_csr_aliasing 5.000s 294.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 31.000s 4780.247us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 298.000s 48512.917us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 928.000s 1109179.032us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 928.000s 1109179.032us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 298.000s 48512.917us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 504.000s 210801.047us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 928.000s 1109179.032us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 2552.365us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 100.000s 16528.384us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 45.921us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 16.574us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 139.575us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 139.575us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 39.302us 1 1 100.00
dma_csr_rw 2.000s 28.261us 1 1 100.00
dma_csr_aliasing 5.000s 294.936us 1 1 100.00
dma_same_csr_outstanding 2.000s 425.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 39.302us 1 1 100.00
dma_csr_rw 2.000s 28.261us 1 1 100.00
dma_csr_aliasing 5.000s 294.936us 1 1 100.00
dma_same_csr_outstanding 2.000s 425.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 21.000s 216.959us 1 1 100.00
dma_generic_stress 504.000s 210801.047us 1 1 100.00
dma_handshake_stress 928.000s 1109179.032us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 1751.817us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 121.724us 1 1 100.00
dma_sec_cm 1.000s 10.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 94.000s 19999.942us 1 1 100.00
dma_longer_transfer 9.000s 334.113us 1 1 100.00
dma_stress_all_with_rand_reset 7.000s 450.925us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 90951535238484534730104060418131006112970715769243063557024371834820145120206 103
UVM_INFO @ 450925102ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---