Simulation Results: edn/edn0

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.87 %
  • code
  • 84.59 %
  • assert
  • 95.80 %
  • func
  • 50.21 %
  • block
  • 94.25 %
  • line
  • 96.98 %
  • branch
  • 87.62 %
  • toggle
  • 73.14 %
  • FSM
  • 80.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 61.106us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 65.098us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 27.012us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 545.584us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 27.728us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 29.895us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 27.012us 1 1 100.00
edn_csr_aliasing 1.000s 27.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 36.858us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 36.858us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 36.858us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 21.663us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 112.438us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 29.167us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 45.033us 1 1 100.00
edn_disable_auto_req_mode 1.000s 99.051us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 242.545us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 20.115us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 28.296us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 76.488us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 76.488us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 65.098us 1 1 100.00
edn_csr_rw 2.000s 27.012us 1 1 100.00
edn_csr_aliasing 1.000s 27.728us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.958us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 65.098us 1 1 100.00
edn_csr_rw 2.000s 27.012us 1 1 100.00
edn_csr_aliasing 1.000s 27.728us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 1052.691us 1 1 100.00
edn_tl_intg_err 2.000s 128.211us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 30.514us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 112.438us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 1052.691us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 1052.691us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 1052.691us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 1052.691us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 112.438us 1 1 100.00
edn_sec_cm 7.000s 1052.691us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 112.438us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 128.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 49.000s 3052.093us 1 1 100.00