Simulation Results: edn/edn1

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.10 %
  • code
  • 82.96 %
  • assert
  • 98.44 %
  • func
  • 76.89 %
  • line
  • 98.03 %
  • branch
  • 93.29 %
  • cond
  • 87.38 %
  • toggle
  • 94.03 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 26.104us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 35.241us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 17.710us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.980s 153.237us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.020s 96.296us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.900s 33.966us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 17.710us 1 1 100.00
edn_csr_aliasing 1.020s 96.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.140s 28.663us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.140s 28.663us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.140s 28.663us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.780s 54.838us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.060s 31.091us 1 1 100.00
errs 1 1 100.00
edn_err 0.970s 29.394us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 12.495us 1 1 100.00
edn_disable_auto_req_mode 0.990s 58.661us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.320s 495.917us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 42.314us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.830s 17.401us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.070s 115.795us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.070s 115.795us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 35.241us 1 1 100.00
edn_csr_rw 0.740s 17.710us 1 1 100.00
edn_csr_aliasing 1.020s 96.296us 1 1 100.00
edn_same_csr_outstanding 0.950s 87.323us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 35.241us 1 1 100.00
edn_csr_rw 0.740s 17.710us 1 1 100.00
edn_csr_aliasing 1.020s 96.296us 1 1 100.00
edn_same_csr_outstanding 0.950s 87.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.690s 194.602us 1 1 100.00
edn_tl_intg_err 2.250s 504.865us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 19.080us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.060s 31.091us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.690s 194.602us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.690s 194.602us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.690s 194.602us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.690s 194.602us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.060s 31.091us 1 1 100.00
edn_sec_cm 2.690s 194.602us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.060s 31.091us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.250s 504.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 96.890s 10762.964us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 53178342245283593100946263684174445093950743919663182291411782485808621176024 165
UVM_INFO @ 10762963712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---