Simulation Results: entropy_src/rng_16bits

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 69.40 %
  • code
  • 82.17 %
  • assert
  • 73.64 %
  • func
  • 52.38 %
  • block
  • 93.96 %
  • line
  • 97.61 %
  • branch
  • 85.86 %
  • toggle
  • 52.50 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
93.75%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 209.323us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 28.896us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 31.399us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 9.000s 438.729us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 259.104us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 84.388us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 31.399us 1 1 100.00
entropy_src_csr_aliasing 3.000s 259.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 209.323us 1 1 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
entropy_src_fw_ov 60.000s 2506.202us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 60.000s 2506.202us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 238.000s 14053.477us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
entropy_src_intr 12.000s 1341.343us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
entropy_src_functional_alerts 5.000s 1318.045us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 307.000s 13301.001us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 109.509us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 38.909us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 64.683us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 21.259us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 47.608us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 47.608us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 28.896us 1 1 100.00
entropy_src_csr_rw 2.000s 31.399us 1 1 100.00
entropy_src_csr_aliasing 3.000s 259.104us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 86.028us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 28.896us 1 1 100.00
entropy_src_csr_rw 2.000s 31.399us 1 1 100.00
entropy_src_csr_aliasing 3.000s 259.104us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 86.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 58.871us 1 1 100.00
entropy_src_tl_intg_err 4.000s 500.189us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
entropy_src_cfg_regwen 1.000s 16.618us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
entropy_src_fw_ov 60.000s 2506.202us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 109.509us 1 1 100.00
entropy_src_sec_cm 3.000s 58.871us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 109.509us 1 1 100.00
entropy_src_sec_cm 3.000s 58.871us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 281.000s 13069.973us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 109.509us 1 1 100.00
entropy_src_sec_cm 3.000s 58.871us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 109.509us 1 1 100.00
entropy_src_sec_cm 3.000s 58.871us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 109.509us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 1318.045us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 500.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 174.000s 14038.025us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* 1 test run
entropy_src_fw_ov 20966292110903476601034861857454493921898492181157263098238105833229337521138 1060
UVM_INFO @ 2506201809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 49809858721514203858949405724093200299716403413766715365363828923200704670704 113
UVM_INFO @ 84388129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---