| V1 |
|
88.89% |
| V2 |
|
88.24% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.490s | 37.395us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.340s | 140.129us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.060s | 61.735us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.010s | 146.104us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.750s | 33.342us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.650s | 50.762us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 4.790s | 3405.180us | 1 | 1 | 100.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| gpio_csr_aliasing | 1.340s | 20.534us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 0.900s | 17.082us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| gpio_csr_rw | 0.650s | 50.762us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.340s | 20.534us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.350s | 37.760us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 0.940s | 140.355us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.940s | 110.345us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.400s | 146.198us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 2.090s | 300.889us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.650s | 85.777us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 5.810s | 369.603us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 7.030s | 1091.072us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.250s | 82.665us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| gpio_stress_all | 20.340s | 4270.555us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.660s | 41.916us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.720s | 52.979us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.030s | 86.358us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.030s | 86.358us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 2 | 4 | 50.00 | |||
| gpio_csr_rw | 0.650s | 50.762us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.340s | 240.545us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 1.340s | 20.534us | 0 | 1 | 0.00 | |
| gpio_csr_hw_reset | 0.750s | 33.342us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 2 | 4 | 50.00 | |||
| gpio_csr_rw | 0.650s | 50.762us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.340s | 240.545us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 1.340s | 20.534us | 0 | 1 | 0.00 | |
| gpio_csr_hw_reset | 0.750s | 33.342us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 1.920s | 556.390us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.070s | 125.837us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.920s | 556.390us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.720s | 14.513us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 0.610s | 1.693us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.690s | 14.781us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) | 1 test run | |||
| gpio_stress_all_with_rand_reset | 111441515001294508076098277005054631466309276634190200636885084891863568791735 | 80 |
UVM_INFO @ 1692597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 99680122959844573244337632970999701647274215083019213468078688535044124138728 | 79 |
UVM_INFO @ 240544973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * | 1 test run | |||
| gpio_csr_aliasing | 69778032206072816353472327297241867360001161139799337725492029115945800700794 | 77 |
UVM_INFO @ 20534320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|