Simulation Results: hmac

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.05 %
  • code
  • 96.07 %
  • assert
  • 97.17 %
  • func
  • 28.92 %
  • block
  • 97.64 %
  • line
  • 98.39 %
  • branch
  • 94.11 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.000s 350.913us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 262.267us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 47.180us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.000s 10335.680us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 600.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 3.000s 20.800us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 47.180us 1 1 100.00
hmac_csr_aliasing 6.000s 600.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 9.000s 687.879us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 84.000s 6721.905us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 377.359us 1 1 100.00
hmac_test_sha384_vectors 426.000s 51800.036us 1 1 100.00
hmac_test_sha512_vectors 24.000s 2701.657us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 259.417us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 234.476us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 383.334us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 22.000s 7857.698us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 8.000s 164.568us 1 1 100.00
error 1 1 100.00
hmac_error 145.000s 14748.753us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 34.000s 3637.730us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.000s 350.913us 1 1 100.00
hmac_long_msg 9.000s 687.879us 1 1 100.00
hmac_back_pressure 84.000s 6721.905us 1 1 100.00
hmac_datapath_stress 8.000s 164.568us 1 1 100.00
hmac_burst_wr 22.000s 7857.698us 1 1 100.00
hmac_stress_all 37.000s 50899.035us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.000s 350.913us 1 1 100.00
hmac_long_msg 9.000s 687.879us 1 1 100.00
hmac_back_pressure 84.000s 6721.905us 1 1 100.00
hmac_datapath_stress 8.000s 164.568us 1 1 100.00
hmac_wipe_secret 34.000s 3637.730us 1 1 100.00
hmac_test_sha256_vectors 10.000s 377.359us 1 1 100.00
hmac_test_sha384_vectors 426.000s 51800.036us 1 1 100.00
hmac_test_sha512_vectors 24.000s 2701.657us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 259.417us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 234.476us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 383.334us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.000s 350.913us 1 1 100.00
hmac_long_msg 9.000s 687.879us 1 1 100.00
hmac_back_pressure 84.000s 6721.905us 1 1 100.00
hmac_datapath_stress 8.000s 164.568us 1 1 100.00
hmac_burst_wr 22.000s 7857.698us 1 1 100.00
hmac_error 145.000s 14748.753us 1 1 100.00
hmac_wipe_secret 34.000s 3637.730us 1 1 100.00
hmac_test_sha256_vectors 10.000s 377.359us 1 1 100.00
hmac_test_sha384_vectors 426.000s 51800.036us 1 1 100.00
hmac_test_sha512_vectors 24.000s 2701.657us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 259.417us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 234.476us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 383.334us 1 1 100.00
hmac_stress_all 37.000s 50899.035us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 37.000s 50899.035us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 14.092us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 33.485us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 675.369us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 675.369us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 262.267us 1 1 100.00
hmac_csr_rw 2.000s 47.180us 1 1 100.00
hmac_csr_aliasing 6.000s 600.541us 1 1 100.00
hmac_same_csr_outstanding 2.000s 35.713us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 262.267us 1 1 100.00
hmac_csr_rw 2.000s 47.180us 1 1 100.00
hmac_csr_aliasing 6.000s 600.541us 1 1 100.00
hmac_same_csr_outstanding 2.000s 35.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 81.857us 1 1 100.00
hmac_tl_intg_err 2.000s 63.925us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 63.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.000s 350.913us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.000s 60.251us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 187.000s 20647.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 201.273us 1 1 100.00