Simulation Results: i2c

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.13 %
  • code
  • 89.94 %
  • assert
  • 97.04 %
  • func
  • 80.40 %
  • block
  • 96.14 %
  • line
  • 95.60 %
  • branch
  • 93.09 %
  • toggle
  • 86.90 %
  • FSM
  • 84.17 %
Validation stages
V1
100.00%
V2
80.49%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 97.000s 1722.365us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 12.000s 1100.482us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 2.000s 25.331us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.000s 19.076us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 6.000s 977.992us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 3.000s 211.504us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 49.318us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.000s 19.076us 1 1 100.00
i2c_csr_aliasing 3.000s 211.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.000s 24.449us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 2.000s 32.635us 0 1 0.00
host_maxperf 0 1 0.00
i2c_host_perf 3602.159s 0.000us 0 1 0.00
host_override 1 1 100.00
i2c_host_override 1.000s 27.955us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 1877.000s 11714.085us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 713.000s 21726.701us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 2.000s 311.886us 1 1 100.00
i2c_host_fifo_fmt_empty 7.000s 876.230us 1 1 100.00
i2c_host_fifo_reset_rx 6.000s 177.399us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 154.000s 3705.556us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 11.000s 631.310us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 3.000s 133.741us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 4.000s 567.324us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 3601.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 6.000s 3466.965us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 13.000s 1811.057us 1 1 100.00
i2c_target_intr_smoke 8.000s 1387.957us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 4.000s 310.507us 1 1 100.00
i2c_target_fifo_reset_tx 3.000s 948.262us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 6.000s 11788.611us 1 1 100.00
i2c_target_stress_rd 13.000s 1811.057us 1 1 100.00
i2c_target_intr_stress_wr 1031.000s 6067.987us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 9.000s 4997.812us 1 1 100.00
target_clock_stretch 0 1 0.00
i2c_target_stretch 27.000s 10012.843us 0 1 0.00
bad_address 1 1 100.00
i2c_target_bad_addr 6.000s 1157.655us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 10.000s 11498.212us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 3.000s 1977.833us 1 1 100.00
i2c_target_fifo_watermarks_tx 2.000s 298.646us 1 1 100.00
host_mode_config_perf 1 2 50.00
i2c_host_perf 3602.159s 0.000us 0 1 0.00
i2c_host_perf_precise 632.000s 5830.234us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 11.000s 631.310us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 5.000s 525.051us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 6.000s 607.912us 1 1 100.00
i2c_target_nack_acqfull_addr 3.000s 1927.954us 1 1 100.00
i2c_target_nack_txstretch 3.000s 163.648us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 7.000s 854.340us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 3.000s 1019.481us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 2.000s 18.716us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 1.000s 17.436us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.000s 174.335us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.000s 174.335us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 2.000s 25.331us 1 1 100.00
i2c_csr_rw 1.000s 19.076us 1 1 100.00
i2c_csr_aliasing 3.000s 211.504us 1 1 100.00
i2c_same_csr_outstanding 2.000s 26.969us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 2.000s 25.331us 1 1 100.00
i2c_csr_rw 1.000s 19.076us 1 1 100.00
i2c_csr_aliasing 3.000s 211.504us 1 1 100.00
i2c_same_csr_outstanding 2.000s 26.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 3.000s 140.661us 1 1 100.00
i2c_sec_cm 2.000s 78.970us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 3.000s 140.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 4.000s 779.604us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 3.000s 115.537us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 6.000s 309.148us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 39365148222480094615856253879557938840333317949628850255056807055405512234276 89
UVM_INFO @ 24448780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 2824198166508794381985282773929109335399120662758909398268690287231941707635 95
UVM_INFO @ 32635396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 104832227365301605717938264936700105451633999803616912922469612791581040254052 98
UVM_INFO @ 309148392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
i2c_host_perf 63122368845421174484583763258301952480005037231013771632966143047503825538841 None
i2c_target_stress_all 97454786887573221436497259495639404932407695876206615728171939661620981917243 None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 21212378025243527297519125952982032666142687307265698749884264377648143413598 93
UVM_INFO @ 567324125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! 1 test run
i2c_target_stretch 41926306776337170653824836350599339367388573373256688686105846740806378922881 87
UVM_INFO @ 10012842764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 65968661355356417838553429422909162769726368747129668586353109766834986783602 87
UVM_INFO @ 115537471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 71752833665604002859906927962086527092795503811607213944009049630530391887498 88
UVM_INFO @ 11498211822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 84573844077196194611767373238084735340455896634260993139711294911825411193792 93
UVM_INFO @ 779603521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 1 test run
i2c_host_mode_toggle 69248660208315327347128442246491747695922015102722810321347208954036565208386 94
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17476