Simulation Results: kmac/unmasked

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.86 %
  • code
  • 88.75 %
  • assert
  • 98.50 %
  • func
  • 91.34 %
  • line
  • 97.28 %
  • branch
  • 94.90 %
  • cond
  • 92.09 %
  • toggle
  • 100.00 %
  • FSM
  • 59.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 21.970s 2091.963us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.940s 16.329us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.020s 41.528us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 16.160s 15036.518us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.970s 275.110us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.320s 84.408us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.020s 41.528us 1 1 100.00
kmac_csr_aliasing 3.970s 275.110us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 39.084us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.230s 71.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1666.590s 40850.831us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 179.140s 11842.766us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 26.420s 2448.947us 1 1 100.00
kmac_test_vectors_sha3_256 24.120s 1153.500us 1 1 100.00
kmac_test_vectors_sha3_384 23.470s 12581.736us 1 1 100.00
kmac_test_vectors_sha3_512 15.020s 1261.648us 1 1 100.00
kmac_test_vectors_shake_128 2271.580s 144965.288us 1 1 100.00
kmac_test_vectors_shake_256 79.870s 1560.895us 1 1 100.00
kmac_test_vectors_kmac 2.880s 114.461us 1 1 100.00
kmac_test_vectors_kmac_xof 2.430s 298.674us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 219.230s 53962.416us 1 1 100.00
app 1 1 100.00
kmac_app 73.170s 11548.552us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 91.250s 13973.012us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 159.030s 42149.396us 1 1 100.00
error 1 1 100.00
kmac_error 68.920s 4608.059us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 1.340s 155.214us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.050s 26.112us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 8.360s 853.211us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 24.260s 12905.244us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 21.720s 11704.903us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.290s 64.346us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 279.490s 26913.040us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.830s 118.682us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.030s 29.602us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.460s 52.950us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.460s 52.950us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.940s 16.329us 1 1 100.00
kmac_csr_rw 1.020s 41.528us 1 1 100.00
kmac_csr_aliasing 3.970s 275.110us 1 1 100.00
kmac_same_csr_outstanding 1.500s 79.733us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.940s 16.329us 1 1 100.00
kmac_csr_rw 1.020s 41.528us 1 1 100.00
kmac_csr_aliasing 3.970s 275.110us 1 1 100.00
kmac_same_csr_outstanding 1.500s 79.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.860s 355.205us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.860s 355.205us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.860s 355.205us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.860s 355.205us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.020s 442.702us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 40.120s 14341.813us 1 1 100.00
kmac_tl_intg_err 4.330s 198.148us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.330s 198.148us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.290s 64.346us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 21.970s 2091.963us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 219.230s 53962.416us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.860s 355.205us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 40.120s 14341.813us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 40.120s 14341.813us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 40.120s 14341.813us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 21.970s 2091.963us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.290s 64.346us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 40.120s 14341.813us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 16.750s 765.915us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 21.970s 2091.963us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 43.270s 12154.737us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 101182802827466981862509403124847075778767521043883786888761693230186751132503 220
UVM_INFO @ 12154737240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---