Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.05 %
  • code
  • 93.02 %
  • assert
  • 96.83 %
  • func
  • 86.31 %
  • block
  • 96.70 %
  • line
  • 97.35 %
  • branch
  • 91.61 %
  • toggle
  • 87.86 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 79.708us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 110.033us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 35.356us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 29.264us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 47.480us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 56.830us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 35.356us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 47.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.000s 139.815us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 4299.735us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 3.000s 13.930us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 65.906us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 2126.794us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_prog_failure 3.000s 65.906us 1 1 100.00
lc_ctrl_errors 7.000s 2126.794us 1 1 100.00
lc_ctrl_security_escalation 5.000s 5786.924us 1 1 100.00
lc_ctrl_jtag_state_failure 11.000s 4498.091us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 733.264us 1 1 100.00
lc_ctrl_jtag_errors 59.000s 3786.593us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 119.435us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 1433.886us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 733.264us 1 1 100.00
lc_ctrl_jtag_errors 59.000s 3786.593us 1 1 100.00
lc_ctrl_jtag_access 9.000s 403.251us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 954.512us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 5.000s 104.240us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 347.785us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 834.191us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 321.095us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 30.108us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 579.946us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 418.782us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.000s 1414.154us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 16.475us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 196.000s 13838.687us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 3.000s 28.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 520.218us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 520.218us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 110.033us 1 1 100.00
lc_ctrl_csr_rw 2.000s 35.356us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 47.480us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 89.418us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 110.033us 1 1 100.00
lc_ctrl_csr_rw 2.000s 35.356us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 47.480us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 89.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 242.704us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 242.704us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 4299.735us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 1374.160us 1 1 100.00
lc_ctrl_sec_cm 5.000s 249.511us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 5786.924us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.000s 139.815us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 1433.886us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1233.603us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1233.603us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 483.158us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 14.000s 3265.377us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 14.000s 3265.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 22.000s 16916.018us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 87368501800573056234928431080380805465392671103254276864280070052391586357593 4913
UVM_INFO @ 13838686505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 72333148127981605996342542708757320137519238607887536308709449906573493711507 734
UVM_INFO @ 16916017528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---