Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.32 %
  • code
  • 93.33 %
  • assert
  • 96.69 %
  • func
  • 86.94 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 87.71 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 81.711us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 18.320us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 17.809us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 60.090us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.126us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 32.839us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 17.809us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 140.979us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 363.384us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 12.569us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 134.640us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 1906.191us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_prog_failure 2.000s 134.640us 1 1 100.00
lc_ctrl_errors 4.000s 1906.191us 1 1 100.00
lc_ctrl_security_escalation 6.000s 470.366us 1 1 100.00
lc_ctrl_jtag_state_failure 26.000s 2637.888us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.000s 487.214us 1 1 100.00
lc_ctrl_jtag_errors 43.000s 2947.142us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 2165.120us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 1607.866us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.000s 487.214us 1 1 100.00
lc_ctrl_jtag_errors 43.000s 2947.142us 1 1 100.00
lc_ctrl_jtag_access 5.000s 472.448us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.000s 5616.692us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 105.361us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 42.077us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 4901.495us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 13.000s 3561.088us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 20.510us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 66.943us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 102.176us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.000s 11165.165us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 36.531us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 126.000s 39653.920us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 44.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 338.576us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 338.576us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 18.320us 1 1 100.00
lc_ctrl_csr_rw 2.000s 17.809us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.126us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 386.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 18.320us 1 1 100.00
lc_ctrl_csr_rw 2.000s 17.809us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.126us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 386.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 121.687us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 121.687us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 363.384us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 1076.228us 1 1 100.00
lc_ctrl_sec_cm 3.000s 402.389us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 470.366us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 140.979us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 1607.866us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 1817.883us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 1817.883us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 1018.461us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 269.411us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 269.411us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 43.000s 2755.553us 1 1 100.00