Simulation Results: mbx

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.92 %
  • code
  • 90.05 %
  • assert
  • 97.05 %
  • func
  • 76.65 %
  • block
  • 95.93 %
  • line
  • 95.40 %
  • branch
  • 89.19 %
  • toggle
  • 85.57 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 43.000s 2361.766us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 15.875us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 14.305us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 162.764us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 21.737us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 15.934us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 14.305us 1 1 100.00
mbx_csr_aliasing 2.000s 21.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 46.000s 10331.792us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 1.000s 23.951us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 38.000s 4307.344us 1 1 100.00
mbx_doe_intr_msg 0 1 0.00
mbx_doe_intr_msg 6.000s 980.978us 0 1 0.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 24.884us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 18.869us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 4.399us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 4.399us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 15.875us 1 1 100.00
mbx_csr_rw 1.000s 14.305us 1 1 100.00
mbx_csr_aliasing 2.000s 21.737us 1 1 100.00
mbx_same_csr_outstanding 2.000s 41.034us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 15.875us 1 1 100.00
mbx_csr_rw 1.000s 14.305us 1 1 100.00
mbx_csr_aliasing 2.000s 21.737us 1 1 100.00
mbx_same_csr_outstanding 2.000s 41.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 86.990us 1 1 100.00
mbx_sec_cm 1.000s 19.782us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 40905074794118196974781183262462792694355840754500238113926103979800146230342 85
TL item was: req: (cip_tl_seq_item@18221) { a_addr: 'h6e4b3534 a_data: 'h230053fb a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'hd4 a_opcode: 'h1 a_user: 'h279e8 d_param: 'h0 d_source: 'hd4 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4398697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 83120039163213972459925188902920924022150323343504458003797694900150558568230 92
TL item was: req: (cip_tl_seq_item@26288) { a_addr: 'he9b70174 a_data: 'ha9cacf69 a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'h6c a_opcode: 'h1 a_user: 'h279b4 d_param: 'h0 d_source: 'h6c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 15933610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 71120314722448121506839436334318876016771529241433216526732996710504799321655 89
UVM_INFO @ 23950861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_doe_intr_msg_vseq.sv:56) [_item] Check failed act_data == data[i] (* [*] vs * [*]) DOE_INTR_MSG_DATA does not have the expected value 1 test run
mbx_doe_intr_msg 110430873714800190275353462193097034004684972268186488733624707102059795501499 83
UVM_INFO @ 980978450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---