Simulation Results: otbn

 
20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.68 %
  • code
  • 95.41 %
  • assert
  • 90.33 %
  • func
  • 98.31 %
  • block
  • 99.42 %
  • line
  • 99.53 %
  • branch
  • 92.80 %
  • toggle
  • 91.75 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 148.653us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 16.169us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 16.148us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 296.206us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 42.840us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 46.370us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 16.148us 1 1 100.00
otbn_csr_aliasing 3.000s 42.840us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 87.000s 1834.759us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 28.000s 334.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 38.000s 1107.821us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 46.000s 447.472us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 38.000s 758.537us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 6.000s 20.941us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 220.078us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 19.822us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 87.159us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 18.624us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 15.764us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 56.872us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 56.872us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 16.169us 1 1 100.00
otbn_csr_rw 4.000s 16.148us 1 1 100.00
otbn_csr_aliasing 3.000s 42.840us 1 1 100.00
otbn_same_csr_outstanding 4.000s 33.863us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 16.169us 1 1 100.00
otbn_csr_rw 4.000s 16.148us 1 1 100.00
otbn_csr_aliasing 3.000s 42.840us 1 1 100.00
otbn_same_csr_outstanding 4.000s 33.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 65.964us 1 1 100.00
otbn_dmem_err 8.000s 55.138us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 7.000s 81.471us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 27.593us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 138.809us 1 1 100.00
otbn_urnd_err 5.000s 26.233us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 64.999us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 87.760us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 17.675us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
otbn_tl_intg_err 12.000s 75.242us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 44.000s 352.077us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 148.653us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 55.138us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 65.964us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 12.000s 75.242us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 220.078us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 65.964us 1 1 100.00
otbn_dmem_err 8.000s 55.138us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 19.822us 1 1 100.00
otbn_illegal_mem_acc 4.000s 64.999us 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 65.964us 1 1 100.00
otbn_dmem_err 8.000s 55.138us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 19.822us 1 1 100.00
otbn_illegal_mem_acc 4.000s 64.999us 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 220.078us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 65.964us 1 1 100.00
otbn_dmem_err 8.000s 55.138us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 19.822us 1 1 100.00
otbn_illegal_mem_acc 4.000s 64.999us 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 13.614us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 68.352us 1 1 100.00
sec_cm_rnd_bus_consistency 0 1 0.00
otbn_rnd_sec_cm 14.000s 71.119us 0 1 0.00
sec_cm_rnd_rng_digest 0 1 0.00
otbn_rnd_sec_cm 14.000s 71.119us 0 1 0.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 60.467us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 12.000s 61.722us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 152.549us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 152.549us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 10.897us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 38.000s 758.537us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 51.166us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 27.028us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 237.000s 5098.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 115.000s 700.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 138.860us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_multi_err 21401364566770916839651217324803041265842143403501328809192307554534218724506 334
UVM_INFO @ 447471564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rnd_sec_cm 42968846852037454906146397333583362628191451975108299485613140666035106680792 123
UVM_INFO @ 71119039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---