Simulation Results

Simulation Results: otp_ctrl

20/05/2026 15:30:25 DVSim: v1.38.1 sha: 9c9e49f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
70.35 %

code
69.07 %

assert
92.75 %

func
49.22 %

line
86.21 %

branch
81.98 %

cond
85.50 %

toggle
57.73 %

FSM
33.95 %

Validation stages

V1		100.00%
V2		55.00%
V2S		66.67%
V3		50.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	1.760s	58.081us	1	1	100.00
smoke				1	1	100.00
	otp_ctrl_smoke	7.150s	6346.980us	1	1	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	3.070s	498.001us	1	1	100.00
csr_rw				1	1	100.00
	otp_ctrl_csr_rw	2.560s	176.525us	1	1	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	5.030s	342.950us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	9.010s	403.276us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	otp_ctrl_csr_mem_rw_with_rand_reset	3.350s	495.931us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	otp_ctrl_csr_rw	2.560s	176.525us	1	1	100.00
	otp_ctrl_csr_aliasing	9.010s	403.276us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.700s	79.779us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.700s	631.361us	1	1	100.00

11/20 passed

55.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				0	1	0.00
	otp_ctrl_partition_walk	130.710s	38467.536us	0	1	0.00
init_fail				1	1	100.00
	otp_ctrl_init_fail	4.800s	695.265us	1	1	100.00
partition_check				0	2	0.00
	otp_ctrl_background_chks	2.230s	55.111us	0	1	0.00
	otp_ctrl_check_fail	12.070s	6366.198us	0	1	0.00
regwen_during_otp_init				0	1	0.00
	otp_ctrl_regwen	7.660s	263.020us	0	1	0.00
partition_lock				0	1	0.00
	otp_ctrl_dai_lock	12.130s	1079.273us	0	1	0.00
interface_key_check				0	1	0.00
	otp_ctrl_parallel_key_req	2.850s	107.971us	0	1	0.00
lc_interactions				1	2	50.00
	otp_ctrl_parallel_lc_req	9.370s	1100.761us	0	1	0.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
otp_dai_errors				1	1	100.00
	otp_ctrl_dai_errs	25.920s	565.640us	1	1	100.00
otp_macro_errors				1	1	100.00
	otp_ctrl_macro_errs	9.800s	876.204us	1	1	100.00
test_access				0	1	0.00
	otp_ctrl_test_access	3.190s	166.185us	0	1	0.00
stress_all				0	1	0.00
	otp_ctrl_stress_all	6.520s	983.278us	0	1	0.00
intr_test				1	1	100.00
	otp_ctrl_intr_test	2.170s	63.201us	1	1	100.00
alert_test				1	1	100.00
	otp_ctrl_alert_test	2.280s	1127.774us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	otp_ctrl_tl_errors	4.250s	321.424us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	otp_ctrl_tl_errors	4.250s	321.424us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	otp_ctrl_csr_hw_reset	3.070s	498.001us	1	1	100.00
	otp_ctrl_csr_rw	2.560s	176.525us	1	1	100.00
	otp_ctrl_csr_aliasing	9.010s	403.276us	1	1	100.00
	otp_ctrl_same_csr_outstanding	3.680s	103.178us	1	1	100.00
tl_d_partial_access				4	4	100.00
	otp_ctrl_csr_hw_reset	3.070s	498.001us	1	1	100.00
	otp_ctrl_csr_rw	2.560s	176.525us	1	1	100.00
	otp_ctrl_csr_aliasing	9.010s	403.276us	1	1	100.00
	otp_ctrl_same_csr_outstanding	3.680s	103.178us	1	1	100.00

V2S

6/9 passed

66.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
tl_intg_err				2	2	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
	otp_ctrl_tl_intg_err	25.700s	3013.136us	1	1	100.00
prim_count_check				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
prim_fsm_check				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	otp_ctrl_tl_intg_err	25.700s	3013.136us	1	1	100.00
sec_cm_secret_mem_scramble				1	1	100.00
	otp_ctrl_smoke	7.150s	6346.980us	1	1	100.00
sec_cm_part_mem_digest				1	1	100.00
	otp_ctrl_smoke	7.150s	6346.980us	1	1	100.00
sec_cm_dai_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_kdi_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_lci_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_part_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_scrmbl_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_timer_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_dai_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_kdi_seed_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_kdi_entropy_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_lci_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_part_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_scrmbl_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_timer_integ_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_timer_cnsty_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_timer_lfsr_redun				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_dai_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_lci_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
sec_cm_kdi_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
sec_cm_part_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
	otp_ctrl_macro_errs	9.800s	876.204us	1	1	100.00
sec_cm_scrmbl_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
sec_cm_timer_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_dai_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_lci_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
sec_cm_kdi_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
sec_cm_part_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
	otp_ctrl_macro_errs	9.800s	876.204us	1	1	100.00
sec_cm_scrmbl_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
sec_cm_timer_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	33.890s	4359.246us	1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_part_data_reg_integrity				1	1	100.00
	otp_ctrl_init_fail	4.800s	695.265us	1	1	100.00
sec_cm_part_data_reg_bkgn_chk				0	1	0.00
	otp_ctrl_check_fail	12.070s	6366.198us	0	1	0.00
sec_cm_part_mem_regren				0	1	0.00
	otp_ctrl_dai_lock	12.130s	1079.273us	0	1	0.00
sec_cm_part_mem_sw_unreadable				0	1	0.00
	otp_ctrl_dai_lock	12.130s	1079.273us	0	1	0.00
sec_cm_part_mem_sw_unwritable				0	1	0.00
	otp_ctrl_dai_lock	12.130s	1079.273us	0	1	0.00
sec_cm_lc_part_mem_sw_noaccess				0	1	0.00
	otp_ctrl_dai_lock	12.130s	1079.273us	0	1	0.00
sec_cm_access_ctrl_mubi				0	1	0.00
	otp_ctrl_dai_lock	12.130s	1079.273us	0	1	0.00
sec_cm_token_valid_ctrl_mubi				1	1	100.00
	otp_ctrl_smoke	7.150s	6346.980us	1	1	100.00
sec_cm_lc_ctrl_intersig_mubi				0	1	0.00
	otp_ctrl_dai_lock	12.130s	1079.273us	0	1	0.00
sec_cm_test_bus_lc_gated				1	1	100.00
	otp_ctrl_smoke	7.150s	6346.980us	1	1	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	302.890s	18050.643us	1	1	100.00
sec_cm_direct_access_config_regwen				0	1	0.00
	otp_ctrl_regwen	7.660s	263.020us	0	1	0.00
sec_cm_check_trigger_config_regwen				1	1	100.00
	otp_ctrl_smoke	7.150s	6346.980us	1	1	100.00
sec_cm_check_config_regwen				1	1	100.00
	otp_ctrl_smoke	7.150s	6346.980us	1	1	100.00
sec_cm_macro_mem_integrity				1	1	100.00
	otp_ctrl_macro_errs	9.800s	876.204us	1	1	100.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				0	1	0.00
	otp_ctrl_low_freq_read	56.600s	21866.726us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	otp_ctrl_stress_all_with_rand_reset	40.770s	19883.486us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.err_code_				5 test runs
	otp_ctrl_background_chks	52054529094439055119834988166082638804689264868534554461381346425243812787426	222	UVM_INFO @ 55111249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	103681692661610843270534136084141422916198698496143130214835054473554130929618	3587	UVM_INFO @ 6366198239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	38802760268123150323648476585146192305692987244457837134488220996523608768458	1544	UVM_INFO @ 107970982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	56956945325904571445898208850130090287833750570749790145503563949214125123261	3450	UVM_INFO @ 166185499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	7258520201227021212793170169152639695410165406642543663801728854019272855924	4298	UVM_INFO @ 983277607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value:				2 test runs
	otp_ctrl_partition_walk	9773798064191572413140198575718893828324635669344241166187572380780923118477	165565	UVM_INFO @ 38467535729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	87095596289434247549285311599929605438846674214607391290878419452585930363326	8486	UVM_INFO @ 263019890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch				1 test run
	otp_ctrl_low_freq_read	113921191471596981382254427592908113327184838307632355941118310086776917728830	89	UVM_INFO @ 21866726087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() \| status_mask) == (item.d_data \| status_mask) (* [] vs []) reg name: status, compare_mask				1 test run
	otp_ctrl_parallel_lc_req	83626807654311991491793863654524884936878267771665397364023380551843653480513	9141	UVM_INFO @ 1100761059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: OtpErr				1 test run
	otp_ctrl_dai_lock	23509606719587996006417559178318767543387446644825930116279017822207773737688	16135	UVM_INFO @ 1079273134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---